[llvm] r314471 - ARM: Fix cases where CSI Restored bit is not cleared
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 28 16:12:06 PDT 2017
Author: matze
Date: Thu Sep 28 16:12:06 2017
New Revision: 314471
URL: http://llvm.org/viewvc/llvm-project?rev=314471&view=rev
Log:
ARM: Fix cases where CSI Restored bit is not cleared
LR is an untypical callee saved register in that it is restored into a
different register (PC) and thus does not live-out of the return block.
This case requires the `Restored` flag in CalleeSavedInfo to be cleared.
This fixes a number of cases where this wasn't handled correctly yet.
Modified:
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=314471&r1=314470&r2=314471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Sep 28 16:12:06 2017
@@ -1053,7 +1053,8 @@ void ARMFrameLowering::emitPopInst(Machi
unsigned LastReg = 0;
bool DeleteRet = false;
for (; i != 0; --i) {
- unsigned Reg = CSI[i-1].getReg();
+ CalleeSavedInfo &Info = CSI[i-1];
+ unsigned Reg = Info.getReg();
if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
// The aligned reloads from area DPRCS2 are not inserted here.
@@ -1066,6 +1067,9 @@ void ARMFrameLowering::emitPopInst(Machi
Reg = ARM::PC;
DeleteRet = true;
LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
+ // We 'restore' LR into PC so it is not live out of the return block:
+ // Clear Restored bit.
+ Info.setRestored(false);
} else
LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
// Fold the return instruction into the LDM.
@@ -1099,13 +1103,6 @@ void ARMFrameLowering::emitPopInst(Machi
MIB.copyImplicitOps(*MI);
MI->eraseFromParent();
}
- // If LR is not restored, mark it in CSI.
- for (CalleeSavedInfo &I : CSI) {
- if (I.getReg() != ARM::LR)
- continue;
- I.setRestored(false);
- break;
- }
}
MI = MIB;
} else if (Regs.size() == 1) {
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=314471&r1=314470&r2=314471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Thu Sep 28 16:12:06 2017
@@ -1909,6 +1909,17 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM
MO.setReg(ARM::PC);
PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
MBB.erase(MBBI);
+ // We now restore LR into PC so it is not live-out of the return block
+ // anymore: Clear the CSI Restored bit.
+ MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
+ // CSI should be fixed after PrologEpilog Insertion
+ assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid");
+ for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
+ if (Info.getReg() == ARM::LR) {
+ Info.setRestored(false);
+ break;
+ }
+ }
return true;
}
}
Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=314471&r1=314470&r2=314471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Sep 28 16:12:06 2017
@@ -876,13 +876,15 @@ restoreCalleeSavedRegisters(MachineBasic
bool NeedsPop = false;
for (unsigned i = CSI.size(); i != 0; --i) {
- unsigned Reg = CSI[i-1].getReg();
+ CalleeSavedInfo &Info = CSI[i-1];
+ unsigned Reg = Info.getReg();
// High registers (excluding lr) have already been dealt with
if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
continue;
if (Reg == ARM::LR) {
+ Info.setRestored(false);
if (MBB.succ_empty()) {
// Special epilogue for vararg functions. See emitEpilogue
if (isVarArg)
Modified: llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir?rev=314471&r1=314470&r2=314471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir Thu Sep 28 16:12:06 2017
@@ -125,7 +125,7 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
body: |
bb.0.entry:
Modified: llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir?rev=314471&r1=314470&r2=314471&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir (original)
+++ llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir Thu Sep 28 16:12:06 2017
@@ -93,7 +93,7 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
jumpTable:
kind: inline
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