[PATCH] D38309: [RegAllocGreedy]: Allow recoloring of done register if it's non-tied
Mikael Holmén via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 28 01:24:13 PDT 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL314388: [RegAllocGreedy]: Allow recoloring of done register if it's non-tied (authored by uabelho).
Changed prior to commit:
https://reviews.llvm.org/D38309?vs=116927&id=116940#toc
Repository:
rL LLVM
https://reviews.llvm.org/D38309
Files:
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Index: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
@@ -2054,6 +2054,15 @@
// Last Chance Recoloring
//===----------------------------------------------------------------------===//
+/// Return true if \p reg has any tied def operand.
+static bool hasTiedDef(MachineRegisterInfo *MRI, unsigned reg) {
+ for (const MachineOperand &MO : MRI->def_operands(reg))
+ if (MO.isTied())
+ return true;
+
+ return false;
+}
+
/// mayRecolorAllInterferences - Check if the virtual registers that
/// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
/// recolored to free \p PhysReg.
@@ -2082,8 +2091,11 @@
LiveInterval *Intf = Q.interferingVRegs()[i - 1];
// If Intf is done and sit on the same register class as VirtReg,
// it would not be recolorable as it is in the same state as VirtReg.
- if ((getStage(*Intf) == RS_Done &&
- MRI->getRegClass(Intf->reg) == CurRC) ||
+ // However, if VirtReg has tied defs and Intf doesn't, then
+ // there is still a point in examining if it can be recolorable.
+ if (((getStage(*Intf) == RS_Done &&
+ MRI->getRegClass(Intf->reg) == CurRC) &&
+ !(hasTiedDef(MRI, VirtReg.reg) && !hasTiedDef(MRI, Intf->reg))) ||
FixedRegisters.count(Intf->reg)) {
DEBUG(dbgs() << "Early abort: the interference is not recolorable.\n");
return false;
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