[PATCH] D38288: [InstCombine] Restrict transforming shared selects using SimplifySelectsFeedingBinaryOp when we cannot simplify the binary op.

[Balaram Makam via Phabricator via llvm-commits]

bmakam updated this revision to Diff 116701.
bmakam retitled this revision from "[InstCombine] Predicate SimplifySelectsFeedingBinaryOp with m_OneUse to reduce code." to "[InstCombine] Restrict transforming shared selects using SimplifySelectsFeedingBinaryOp when we cannot simplify the binary op.".
bmakam edited the summary of this revision.
bmakam added a comment.

Address Chad's testcase.


https://reviews.llvm.org/D38288

Files:
  lib/Transforms/InstCombine/InstructionCombining.cpp
  test/Transforms/InstCombine/select_arithmetic.ll


Index: test/Transforms/InstCombine/select_arithmetic.ll
===================================================================
--- test/Transforms/InstCombine/select_arithmetic.ll
+++ test/Transforms/InstCombine/select_arithmetic.ll
@@ -38,3 +38,31 @@
 ; CHECK: ret float %tmp2
 }
 
+declare void @use_float(float)
+; Tests folding constants if the selects have multiple uses but
+; we can fold away the binary op with a select.
+define float @test4(i1 zeroext %arg) #0 {
+  %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
+  %tmp1 = select i1 %arg, float 1.000000e+00, float 9.000000e+00
+  %tmp2 = fmul float %tmp, %tmp1
+  call void @use_float(float %tmp)
+  ret float %tmp2
+; CHECK-LABEL: @test4(
+; CHECK: select i1 %arg, float 5.000000e+00, float 6.000000e+00
+; CHECK-NEXT: select i1 %arg, float 5.000000e+00, float 5.400000e+01
+; CHECK-NEXT: call void @use_float(float %tmp)
+; CHECK: ret float %tmp2
+}
+
+; Tests not folding constants if we cannot fold away any of the selects.
+define float @test5(i1 zeroext %arg, float %div) {
+  %tmp = select i1 %arg, float %div, float 5.000000e+00
+  %mul = fmul contract float %tmp, %tmp
+  call void @use_float(float %tmp)
+  ret float %mul
+; CHECK-LABEL: @test5(
+; CHECK: [[TMP:%.*]] = select i1 %arg, float %div, float 5.000000e+00
+; CHECK-NEXT: [[MUL:%.*]] = fmul contract float [[TMP]], [[TMP]]
+; CHECK-NOT: fmul contract float %div, %div
+; CHECK: ret float [[MUL]]
+}
Index: lib/Transforms/InstCombine/InstructionCombining.cpp
===================================================================
--- lib/Transforms/InstCombine/InstructionCombining.cpp
+++ lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -739,9 +739,9 @@
     Value *V2 = SimplifyBinOp(Opcode, B, D, SQ.getWithInstruction(&I));
     if (V1 && V2)
       SI = Builder.CreateSelect(A, V2, V1);
-    else if (V2)
+    else if (LHS->hasOneUse() && RHS->hasOneUse() && V2)
       SI = Builder.CreateSelect(A, V2, Builder.CreateBinOp(Opcode, C, E));
-    else if (V1)
+    else if (LHS->hasOneUse() && RHS->hasOneUse() && V1)
       SI = Builder.CreateSelect(A, Builder.CreateBinOp(Opcode, B, D), V1);
 
     if (SI)


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