[PATCH] D35625: Removal of microMIPS64R6

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Can you also remove the instruction mappings for the R6 variants of dbitswap, dclo, dclz, dlsa, lld, lwupc and ldpc ?



================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:102
 let AdditionalPredicates = [NotInMicroMips] in {
   def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
                                        II_DADDIU, immSExt16, add>,
----------------
This instruction no longer has a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.


================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:123-129
   def DADD   : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>,
                ADD_FM<0, 0x2c>, ISA_MIPS3;
   def DADDu  : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
                ADD_FM<0, 0x2d>, ISA_MIPS3;
   def DSUBu  : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
                ISA_MIPS3;
   def DSUB   : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
----------------
These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.


================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:144-178
   def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
                                           shl, immZExt6>,
              SRA_FM<0x38, 0>, ISA_MIPS3;
   def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
                                           srl, immZExt6>,
              SRA_FM<0x3a, 0>, ISA_MIPS3;
   def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
----------------
These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.


================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:194-201
 let AdditionalPredicates = [NotInMicroMips] in {
   def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
             LW_FM<0x27>, ISA_MIPS3;
   def LD  : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
             LW_FM<0x37>, ISA_MIPS3;
   def SD  : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
             LW_FM<0x3f>, ISA_MIPS3;
----------------
These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.


================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:224
 let AdditionalPredicates = [NotInMicroMips] in {
   def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
             ISA_MIPS3_NOT_32R6_64R6;
----------------
This instruction no longer has a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.


================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:302-305
   def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>,
              CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
   def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>,
              CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
----------------
These instructions no longer have a corresponding microMIPSR6 mapping, so StdMMR6Rel can be removed here.


Repository:
  rL LLVM

https://reviews.llvm.org/D35625