[PATCH] D37328: [mips] Reordering callseq* nodes to be linear

[Simon Dardis via Phabricator via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM with nits addressed.



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Comment at: test/CodeGen/Mips/callseq_order.ll:1
+; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32 -o /dev/null    \
+; RUN:     -verify-machineinstrs -stop-before=expand-isel-pseudos \
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You can drop the CPU specification portion of the llc invocations here, the defaults of 32r2 and 64r2 should sufficient to test the logic that has been changed.


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Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:271
 
-  ; MM32:           lw      $25, %call16(__multi3)($16)
+  ; MM32:           lw      $25, %call16(__multi3)($[[T0:[0-9]+]])
 
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You don't need to bind the register number to a FileCheck variable in this case, as it's unused afterwards. Either match it with {{[0-9a-z]+}} or drop the register portion as we're interested in matching the:

   lw $25, %call16(__multi3)

part of the instruction. This applies to the following test changes as well.


Repository:
  rL LLVM

https://reviews.llvm.org/D37328