[PATCH] D38275: [X86] Remove dead code from X86DAGToDAGISel's handling of DIV

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 26 15:30:53 PDT 2017


craig.topper created this revision.
Herald added a subscriber: igorb.

The code for handling UDIVREM8_ZEXT_HREG with a 64-bit result type has been dead since r256924.

Though I'm not entirely sure it should be dead. The output from the test case from that revision shows an extra movzx that we could get rid of if this code was live. So I'm posting this patch to start a conversation

  define i64 @pr25754(i8 %a, i8 %c) {
  ; X32-LABEL: pr25754:
  ; X32:       # BB#0:
  ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
  ; X32-NEXT:    # kill: %EAX<def> %EAX<kill> %AX<def>
  ; X32-NEXT:    divb {{[0-9]+}}(%esp)
  ; X32-NEXT:    movzbl %ah, %ecx
  ; X32-NEXT:    movzbl %al, %eax
  ; X32-NEXT:    addl %ecx, %eax
  ; X32-NEXT:    xorl %edx, %edx
  ; X32-NEXT:    retl
  ;
  ; X64-LABEL: pr25754:
  ; X64:       # BB#0:
  ; X64-NEXT:    movzbl %dil, %eax
  ; X64-NEXT:    # kill: %EAX<def> %EAX<kill> %AX<def>
  ; X64-NEXT:    divb %sil
  ; X64-NEXT:    movzbl %ah, %ecx
  ; X64-NEXT:    movzbl %cl, %ecx
  ; X64-NEXT:    movzbl %al, %eax
  ; X64-NEXT:    addq %rcx, %rax
  ; X64-NEXT:    retq
    %r1 = urem i8 %a, %c
    %d1 = udiv i8 %a, %c
    %r2 = zext i8 %r1 to i64
    %d2 = zext i8 %d1 to i64
    %ret = add i64 %r2, %d2
    ret i64 %ret
  }


https://reviews.llvm.org/D38275

Files:
  lib/Target/X86/X86ISelDAGToDAG.cpp


Index: lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- lib/Target/X86/X86ISelDAGToDAG.cpp
+++ lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2886,19 +2886,7 @@
 
       if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
           Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
-        if (Node->getValueType(1) == MVT::i64) {
-          // It's not possible to directly movsx AH to a 64bit register, because
-          // the latter needs the REX prefix, but the former can't have it.
-          assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
-                 "Unexpected i64 sext of h-register");
-          Result =
-              SDValue(CurDAG->getMachineNode(
-                          TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
-                          CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
-                          CurDAG->getTargetConstant(X86::sub_32bit, dl,
-                                                    MVT::i32)),
-                      0);
-        }
+        assert(Node->getValueType(1) == MVT::i32 && "Unexpected type!");
       } else {
         Result =
             CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);


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