[PATCH] D36454: [X86] Changes to extract Horizontal addition operation for AVX-512.

[Jatin Bhateja via Phabricator via llvm-commits]

jbhateja added a comment.

In https://reviews.llvm.org/D36454#876132, @craig.topper wrote:

> I don't think we should shrinking operations based on undef inputs. I think we should be shrinking them based on what elements are consumed by their users. There's no reason the shuffles in these reductions have to have undef elements. For integers we may rewrite the shuffle mask to undef in InstCombine if the elements aren't used down stream. But we don't do that for FP.
>
> As an example, why shouldn't we be able use a horizontal add for this
>
>   define <4 x double> @fadd_noundef(<8 x double> %x225, <8 x double> %x227) {
>  
>     %x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
>     %x228 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5 ,i32 13, i32 7, i32 15>
>     %x229 = fadd <8 x double> %x226, %x228
>     %x230 = shufflevector <8 x double> %x229, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
>     ret <4 x double> %x230
>   }
>


We do generate horizontal addition in this case.



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:1700
 
+typedef enum : unsigned { MMX = 0, XMM = 1, YMM = 3, ZMM = 7 } VecRegKind;
+enum : unsigned { UNDEF, FRWD, BKWD };
----------------
craig.topper wrote:
> Use of MMX here is weird. We explicitly don't generate any optimized code for MMX. So making references to it in terms of SSE/AVX is misleading.
Reference to MMX here is  signifying  one of the denominations of a smaller vector register. 


https://reviews.llvm.org/D36454