[llvm] r314151 - [X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 26 03:27:29 PDT 2017
This crashes llc when printing assembly and I'm also seeing
miscompiles, probably for the same reason. Reverted for now in
r314199.
test case, there should be a movb %ah, %cl in the output:
$ cat bug.ll
define void @foo(i32* %ptr) noinline optnone uwtable {
entry:
%0 = load i32, i32* %ptr, align 4
%and54 = and i32 %0, 65280
%shr = ashr i32 %and54, 8
switch i32 %shr, label %sw.default [
i32 0, label %sw.bb
]
sw.bb: ; preds = %if.end15
unreachable
sw.default: ; preds = %if.end15
unreachable
}
$ llc -O0 < bug.ll
llc: lib/Target/X86/X86GenAsmWriter.inc:45889: void
llvm::X86ATTInstPrinter::printInstruction(const llvm::MCInst *,
llvm::raw_ostream &): Assertion `Bits != 0 && "Cannot print this
instruction."' failed.
On Mon, Sep 25, 2017 at 11:14 PM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Mon Sep 25 14:14:55 2017
> New Revision: 314151
>
> URL: http://llvm.org/viewvc/llvm-project?rev=314151&view=rev
> Log:
> [X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86InstrExtension.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
> llvm/trunk/test/CodeGen/X86/bmi.ll
> llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll
> llvm/trunk/test/CodeGen/X86/divrem.ll
> llvm/trunk/test/CodeGen/X86/divrem8_ext.ll
> llvm/trunk/test/CodeGen/X86/extract-store.ll
> llvm/trunk/test/CodeGen/X86/popcnt.ll
> llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
> llvm/trunk/test/CodeGen/X86/urem-power-of-two.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Mon Sep 25 14:14:55 2017
> @@ -94,26 +94,22 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (out
> // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
> // except that they use GR32_NOREX for the output operand register class
> // instead of GR32. This allows them to operate on h registers on x86-64.
> -let hasSideEffects = 0, isCodeGenOnly = 1 in {
> -def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
> +let hasSideEffects = 0, isPseudo = 1 in {
> +def MOVZX32_NOREXrr8 : I<0, Pseudo,
> (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
> - "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
> - [], IIC_MOVZX>, TB, OpSize32, Sched<[WriteALU]>;
> + "", [], IIC_MOVZX>, Sched<[WriteALU]>;
> let mayLoad = 1 in
> -def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
> +def MOVZX32_NOREXrm8 : I<0, Pseudo,
> (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
> - "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
> - [], IIC_MOVZX>, TB, OpSize32, Sched<[WriteALULd]>;
> + "", [], IIC_MOVZX>, Sched<[WriteALULd]>;
>
> -def MOVSX32_NOREXrr8 : I<0xBE, MRMSrcReg,
> +def MOVSX32_NOREXrr8 : I<0, Pseudo,
> (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
> - "movs{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
> - [], IIC_MOVSX>, TB, OpSize32, Sched<[WriteALU]>;
> + "", [], IIC_MOVSX>, Sched<[WriteALU]>;
> let mayLoad = 1 in
> -def MOVSX32_NOREXrm8 : I<0xBE, MRMSrcMem,
> +def MOVSX32_NOREXrm8 : I<0, Pseudo,
> (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
> - "movs{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
> - [], IIC_MOVSX>, TB, OpSize32, Sched<[WriteALULd]>;
> + "", [], IIC_MOVSX>, Sched<[WriteALULd]>;
> }
>
> // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Sep 25 14:14:55 2017
> @@ -7888,6 +7888,27 @@ bool X86InstrInfo::expandPostRAPseudo(Ma
> case X86::VMOVUPSZ256mr_NOVLX:
> return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
> get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
> + case X86::MOV8rr_NOREX:
> + MI.setDesc(get(X86::MOV8rr));
> + return true;
> + case X86::MOV8rm_NOREX:
> + MI.setDesc(get(X86::MOV8rm));
> + return true;
> + case X86::MOV8mr_NOREX:
> + MI.setDesc(get(X86::MOV8mr));
> + return true;
> + case X86::MOVZX32_NOREXrr8:
> + MI.setDesc(get(X86::MOVZX32rr8));
> + return true;
> + case X86::MOVZX32_NOREXrm8:
> + MI.setDesc(get(X86::MOVZX32rm8));
> + return true;
> + case X86::MOVSX32_NOREXrr8:
> + MI.setDesc(get(X86::MOVSX32rr8));
> + return true;
> + case X86::MOVSX32_NOREXrm8:
> + MI.setDesc(get(X86::MOVSX32rm8));
> + return true;
> case X86::TEST8ri_NOREX:
> MI.setDesc(get(X86::TEST8ri));
> return true;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep 25 14:14:55 2017
> @@ -1618,23 +1618,20 @@ def MOV64mr : RI<0x89, MRMDestMem, (outs
> // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
> // that they can be used for copying and storing h registers, which can't be
> // encoded when a REX prefix is present.
> -let isCodeGenOnly = 1 in {
> +let isPseudo = 1 in {
> let hasSideEffects = 0 in
> -def MOV8rr_NOREX : I<0x88, MRMDestReg,
> +def MOV8rr_NOREX : I<0, Pseudo,
> (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
> - "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
> - Sched<[WriteMove]>;
> + "", [], IIC_MOV>, Sched<[WriteMove]>;
> let mayStore = 1, hasSideEffects = 0 in
> -def MOV8mr_NOREX : I<0x88, MRMDestMem,
> +def MOV8mr_NOREX : I<0, Pseudo,
> (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
> - "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
> - IIC_MOV_MEM>, Sched<[WriteStore]>;
> + "", [], IIC_MOV_MEM>, Sched<[WriteStore]>;
> let mayLoad = 1, hasSideEffects = 0,
> canFoldAsLoad = 1, isReMaterializable = 1 in
> -def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
> +def MOV8rm_NOREX : I<0, Pseudo,
> (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
> - "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
> - IIC_MOV_MEM>, Sched<[WriteLoad]>;
> + "", [], IIC_MOV_MEM>, Sched<[WriteLoad]>;
> }
>
>
>
> Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Mon Sep 25 14:14:55 2017
> @@ -604,9 +604,7 @@ ReSimplify:
> // Note, we are currently not handling the following instructions:
> // MOV64ao8, MOV64o8a
> // XCHG16ar, XCHG32ar, XCHG64ar
> - case X86::MOV8mr_NOREX:
> case X86::MOV8mr:
> - case X86::MOV8rm_NOREX:
> case X86::MOV8rm:
> case X86::MOV16mr:
> case X86::MOV16rm:
> @@ -615,9 +613,7 @@ ReSimplify:
> unsigned NewOpc;
> switch (OutMI.getOpcode()) {
> default: llvm_unreachable("Invalid opcode");
> - case X86::MOV8mr_NOREX:
> case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
> - case X86::MOV8rm_NOREX:
> case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
> case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
> case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
>
> Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/bmi.ll Mon Sep 25 14:14:55 2017
> @@ -316,7 +316,7 @@ define i32 @bextr32_subreg(i32 %x) uwta
> ; CHECK-LABEL: bextr32_subreg:
> ; CHECK: # BB#0:
> ; CHECK-NEXT: movl %edi, %eax
> -; CHECK-NEXT: movzbl %ah, %eax # NOREX
> +; CHECK-NEXT: movzbl %ah, %eax
> ; CHECK-NEXT: retq
> %1 = lshr i32 %x, 8
> %2 = and i32 %1, 255
> @@ -374,7 +374,7 @@ define i64 @bextr64_subreg(i64 %x) uwta
> ; CHECK-LABEL: bextr64_subreg:
> ; CHECK: # BB#0:
> ; CHECK-NEXT: movq %rdi, %rax
> -; CHECK-NEXT: movzbl %ah, %eax # NOREX
> +; CHECK-NEXT: movzbl %ah, %eax
> ; CHECK-NEXT: retq
> %1 = lshr i64 %x, 8
> %2 = and i64 %1, 255
>
> Modified: llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll Mon Sep 25 14:14:55 2017
> @@ -43,7 +43,7 @@ define i32 @Test_get_remainder(i32 %a, i
> ; CHECK-NEXT: movzbl %al, %eax
> ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; CHECK-NEXT: divb %cl
> -; CHECK-NEXT: movzbl %ah, %eax # NOREX
> +; CHECK-NEXT: movzbl %ah, %eax
> ; CHECK-NEXT: retl
> %result = srem i32 %a, %b
> ret i32 %result
> @@ -67,7 +67,7 @@ define i32 @Test_get_quotient_and_remain
> ; CHECK-NEXT: movzbl %al, %eax
> ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; CHECK-NEXT: divb %cl
> -; CHECK-NEXT: movzbl %ah, %edx # NOREX
> +; CHECK-NEXT: movzbl %ah, %edx
> ; CHECK-NEXT: movzbl %al, %eax
> ; CHECK-NEXT: addl %edx, %eax
> ; CHECK-NEXT: retl
>
> Modified: llvm/trunk/test/CodeGen/X86/divrem.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divrem.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/divrem.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/divrem.ll Mon Sep 25 14:14:55 2017
> @@ -122,7 +122,7 @@ define void @si8(i8 %x, i8 %y, i8* %p, i
> ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
> ; X32-NEXT: cbtw
> ; X32-NEXT: idivb {{[0-9]+}}(%esp)
> -; X32-NEXT: movsbl %ah, %ebx # NOREX
> +; X32-NEXT: movsbl %ah, %ebx
> ; X32-NEXT: movb %al, (%edx)
> ; X32-NEXT: movb %bl, (%ecx)
> ; X32-NEXT: popl %ebx
> @@ -133,7 +133,7 @@ define void @si8(i8 %x, i8 %y, i8* %p, i
> ; X64-NEXT: movl %edi, %eax
> ; X64-NEXT: cbtw
> ; X64-NEXT: idivb %sil
> -; X64-NEXT: movsbl %ah, %esi # NOREX
> +; X64-NEXT: movsbl %ah, %esi
> ; X64-NEXT: movb %al, (%rdx)
> ; X64-NEXT: movb %sil, (%rcx)
> ; X64-NEXT: retq
> @@ -264,7 +264,7 @@ define void @ui8(i8 %x, i8 %y, i8* %p, i
> ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X32-NEXT: divb {{[0-9]+}}(%esp)
> -; X32-NEXT: movzbl %ah, %ebx # NOREX
> +; X32-NEXT: movzbl %ah, %ebx
> ; X32-NEXT: movb %al, (%edx)
> ; X32-NEXT: movb %bl, (%ecx)
> ; X32-NEXT: popl %ebx
> @@ -275,7 +275,7 @@ define void @ui8(i8 %x, i8 %y, i8* %p, i
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %esi # NOREX
> +; X64-NEXT: movzbl %ah, %esi
> ; X64-NEXT: movb %al, (%rdx)
> ; X64-NEXT: movb %sil, (%rcx)
> ; X64-NEXT: retq
>
> Modified: llvm/trunk/test/CodeGen/X86/divrem8_ext.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divrem8_ext.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/divrem8_ext.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/divrem8_ext.ll Mon Sep 25 14:14:55 2017
> @@ -8,7 +8,7 @@ define zeroext i8 @test_udivrem_zext_ah(
> ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X32-NEXT: divb {{[0-9]+}}(%esp)
> -; X32-NEXT: movzbl %ah, %ecx # NOREX
> +; X32-NEXT: movzbl %ah, %ecx
> ; X32-NEXT: movb %al, z
> ; X32-NEXT: movl %ecx, %eax
> ; X32-NEXT: retl
> @@ -18,7 +18,7 @@ define zeroext i8 @test_udivrem_zext_ah(
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %ecx # NOREX
> +; X64-NEXT: movzbl %ah, %ecx
> ; X64-NEXT: movb %al, {{.*}}(%rip)
> ; X64-NEXT: movl %ecx, %eax
> ; X64-NEXT: retq
> @@ -34,7 +34,7 @@ define zeroext i8 @test_urem_zext_ah(i8
> ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X32-NEXT: divb {{[0-9]+}}(%esp)
> -; X32-NEXT: movzbl %ah, %eax # NOREX
> +; X32-NEXT: movzbl %ah, %eax
> ; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X32-NEXT: retl
> ;
> @@ -43,7 +43,7 @@ define zeroext i8 @test_urem_zext_ah(i8
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %eax # NOREX
> +; X64-NEXT: movzbl %ah, %eax
> ; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X64-NEXT: retq
> %1 = urem i8 %x, %y
> @@ -57,7 +57,7 @@ define i8 @test_urem_noext_ah(i8 %x, i8
> ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X32-NEXT: divb %cl
> -; X32-NEXT: movzbl %ah, %eax # NOREX
> +; X32-NEXT: movzbl %ah, %eax
> ; X32-NEXT: addb %cl, %al
> ; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X32-NEXT: retl
> @@ -67,7 +67,7 @@ define i8 @test_urem_noext_ah(i8 %x, i8
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %eax # NOREX
> +; X64-NEXT: movzbl %ah, %eax
> ; X64-NEXT: addb %sil, %al
> ; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X64-NEXT: retq
> @@ -82,7 +82,7 @@ define i64 @test_urem_zext64_ah(i8 %x, i
> ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X32-NEXT: divb {{[0-9]+}}(%esp)
> -; X32-NEXT: movzbl %ah, %eax # NOREX
> +; X32-NEXT: movzbl %ah, %eax
> ; X32-NEXT: xorl %edx, %edx
> ; X32-NEXT: retl
> ;
> @@ -91,7 +91,7 @@ define i64 @test_urem_zext64_ah(i8 %x, i
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %eax # NOREX
> +; X64-NEXT: movzbl %ah, %eax
> ; X64-NEXT: movzbl %al, %eax
> ; X64-NEXT: retq
> %1 = urem i8 %x, %y
> @@ -105,7 +105,7 @@ define signext i8 @test_sdivrem_sext_ah(
> ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
> ; X32-NEXT: cbtw
> ; X32-NEXT: idivb {{[0-9]+}}(%esp)
> -; X32-NEXT: movsbl %ah, %ecx # NOREX
> +; X32-NEXT: movsbl %ah, %ecx
> ; X32-NEXT: movb %al, z
> ; X32-NEXT: movl %ecx, %eax
> ; X32-NEXT: retl
> @@ -115,7 +115,7 @@ define signext i8 @test_sdivrem_sext_ah(
> ; X64-NEXT: movl %edi, %eax
> ; X64-NEXT: cbtw
> ; X64-NEXT: idivb %sil
> -; X64-NEXT: movsbl %ah, %ecx # NOREX
> +; X64-NEXT: movsbl %ah, %ecx
> ; X64-NEXT: movb %al, {{.*}}(%rip)
> ; X64-NEXT: movl %ecx, %eax
> ; X64-NEXT: retq
> @@ -131,7 +131,7 @@ define signext i8 @test_srem_sext_ah(i8
> ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
> ; X32-NEXT: cbtw
> ; X32-NEXT: idivb {{[0-9]+}}(%esp)
> -; X32-NEXT: movsbl %ah, %eax # NOREX
> +; X32-NEXT: movsbl %ah, %eax
> ; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X32-NEXT: retl
> ;
> @@ -140,7 +140,7 @@ define signext i8 @test_srem_sext_ah(i8
> ; X64-NEXT: movl %edi, %eax
> ; X64-NEXT: cbtw
> ; X64-NEXT: idivb %sil
> -; X64-NEXT: movsbl %ah, %eax # NOREX
> +; X64-NEXT: movsbl %ah, %eax
> ; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X64-NEXT: retq
> %1 = srem i8 %x, %y
> @@ -154,7 +154,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8
> ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
> ; X32-NEXT: cbtw
> ; X32-NEXT: idivb %cl
> -; X32-NEXT: movsbl %ah, %eax # NOREX
> +; X32-NEXT: movsbl %ah, %eax
> ; X32-NEXT: addb %cl, %al
> ; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X32-NEXT: retl
> @@ -164,7 +164,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8
> ; X64-NEXT: movl %edi, %eax
> ; X64-NEXT: cbtw
> ; X64-NEXT: idivb %sil
> -; X64-NEXT: movsbl %ah, %eax # NOREX
> +; X64-NEXT: movsbl %ah, %eax
> ; X64-NEXT: addb %sil, %al
> ; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X64-NEXT: retq
> @@ -179,7 +179,7 @@ define i64 @test_srem_sext64_ah(i8 %x, i
> ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
> ; X32-NEXT: cbtw
> ; X32-NEXT: idivb {{[0-9]+}}(%esp)
> -; X32-NEXT: movsbl %ah, %eax # NOREX
> +; X32-NEXT: movsbl %ah, %eax
> ; X32-NEXT: movl %eax, %edx
> ; X32-NEXT: sarl $31, %edx
> ; X32-NEXT: retl
> @@ -189,7 +189,7 @@ define i64 @test_srem_sext64_ah(i8 %x, i
> ; X64-NEXT: movl %edi, %eax
> ; X64-NEXT: cbtw
> ; X64-NEXT: idivb %sil
> -; X64-NEXT: movsbl %ah, %eax # NOREX
> +; X64-NEXT: movsbl %ah, %eax
> ; X64-NEXT: movsbq %al, %rax
> ; X64-NEXT: retq
> %1 = srem i8 %x, %y
> @@ -203,7 +203,7 @@ define i64 @pr25754(i8 %a, i8 %c) {
> ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X32-NEXT: divb {{[0-9]+}}(%esp)
> -; X32-NEXT: movzbl %ah, %ecx # NOREX
> +; X32-NEXT: movzbl %ah, %ecx
> ; X32-NEXT: movzbl %al, %eax
> ; X32-NEXT: addl %ecx, %eax
> ; X32-NEXT: xorl %edx, %edx
> @@ -214,7 +214,7 @@ define i64 @pr25754(i8 %a, i8 %c) {
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %ecx # NOREX
> +; X64-NEXT: movzbl %ah, %ecx
> ; X64-NEXT: movzbl %cl, %ecx
> ; X64-NEXT: movzbl %al, %eax
> ; X64-NEXT: addq %rcx, %rax
>
> Modified: llvm/trunk/test/CodeGen/X86/extract-store.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extract-store.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/extract-store.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/extract-store.ll Mon Sep 25 14:14:55 2017
> @@ -114,7 +114,7 @@ define void @extract_i8_15(i8* nocapture
> ; SSE2-X64-LABEL: extract_i8_15:
> ; SSE2-X64: # BB#0:
> ; SSE2-X64-NEXT: pextrw $7, %xmm0, %eax
> -; SSE2-X64-NEXT: movb %ah, (%rdi) # NOREX
> +; SSE2-X64-NEXT: movb %ah, (%rdi)
> ; SSE2-X64-NEXT: retq
> ;
> ; SSE41-X32-LABEL: extract_i8_15:
> @@ -142,7 +142,7 @@ define void @extract_i8_15(i8* nocapture
> ; SSE-F128-LABEL: extract_i8_15:
> ; SSE-F128: # BB#0:
> ; SSE-F128-NEXT: pextrw $7, %xmm0, %eax
> -; SSE-F128-NEXT: movb %ah, (%rdi) # NOREX
> +; SSE-F128-NEXT: movb %ah, (%rdi)
> ; SSE-F128-NEXT: retq
> %vecext = extractelement <16 x i8> %foo, i32 15
> store i8 %vecext, i8* %dst, align 1
>
> Modified: llvm/trunk/test/CodeGen/X86/popcnt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/popcnt.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/popcnt.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/popcnt.ll Mon Sep 25 14:14:55 2017
> @@ -101,7 +101,7 @@ define i16 @cnt16(i16 %x) nounwind readn
> ; X64-NEXT: movl %eax, %ecx
> ; X64-NEXT: shll $8, %ecx
> ; X64-NEXT: addl %eax, %ecx
> -; X64-NEXT: movzbl %ch, %eax # NOREX
> +; X64-NEXT: movzbl %ch, %eax
> ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
> ; X64-NEXT: retq
> ;
>
> Modified: llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tbm_patterns.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tbm_patterns.ll Mon Sep 25 14:14:55 2017
> @@ -18,7 +18,7 @@ define i32 @test_x86_tbm_bextri_u32_subr
> ; CHECK-LABEL: test_x86_tbm_bextri_u32_subreg:
> ; CHECK: # BB#0:
> ; CHECK-NEXT: movl %edi, %eax
> -; CHECK-NEXT: movzbl %ah, %eax # NOREX
> +; CHECK-NEXT: movzbl %ah, %eax
> ; CHECK-NEXT: retq
> %t0 = lshr i32 %a, 8
> %t1 = and i32 %t0, 255
> @@ -79,7 +79,7 @@ define i64 @test_x86_tbm_bextri_u64_subr
> ; CHECK-LABEL: test_x86_tbm_bextri_u64_subreg:
> ; CHECK: # BB#0:
> ; CHECK-NEXT: movq %rdi, %rax
> -; CHECK-NEXT: movzbl %ah, %eax # NOREX
> +; CHECK-NEXT: movzbl %ah, %eax
> ; CHECK-NEXT: retq
> %t0 = lshr i64 %a, 8
> %t1 = and i64 %t0, 255
>
> Modified: llvm/trunk/test/CodeGen/X86/urem-power-of-two.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/urem-power-of-two.ll?rev=314151&r1=314150&r2=314151&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/urem-power-of-two.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/urem-power-of-two.ll Mon Sep 25 14:14:55 2017
> @@ -83,7 +83,7 @@ define i8 @and_pow_2(i8 %x, i8 %y) {
> ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
> ; X86-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X86-NEXT: divb %cl
> -; X86-NEXT: movzbl %ah, %eax # NOREX
> +; X86-NEXT: movzbl %ah, %eax
> ; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X86-NEXT: retl
> ;
> @@ -93,7 +93,7 @@ define i8 @and_pow_2(i8 %x, i8 %y) {
> ; X64-NEXT: movzbl %dil, %eax
> ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
> ; X64-NEXT: divb %sil
> -; X64-NEXT: movzbl %ah, %eax # NOREX
> +; X64-NEXT: movzbl %ah, %eax
> ; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
> ; X64-NEXT: retq
> %and = and i8 %y, 4
>
>
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