[PATCH] D38175: [ARM] Make sure assembler rejects PC as an operand for VMOV.F16

[Andre Vieira via Phabricator via llvm-commits]

avieira added a comment.

I took the opportunity to also look at the SP operand. Currently it is not rejected either, and it should for non Armv8-A architectures running in Thumb mode.

Now I am looking at rGPR for this, but GPR rejects SP for non Armv8-A Arm mode too, and that is not what we want here. I am now investigating further, to see whether it would make sense to actually change the behavior of rGPR to reflect the behavior we need and I found an instruction that is using rGPR but I dont think it should. The VLD1LNd8_UPD instruction, has the third Rm operand down as a rGPR, but that means it would accept SP for Armv8-A architectures and that conflicts with what I am seeing in the Armv8-A ARM ARM. The only variants of VLD{1,2,4,5} that use Rm as an operand in the instruction do not accept Rm to be either SP or PC, these are encodings reserved for the offset and post-indexed variants. So I'm guessing this breaks the current use of rGPR already.

All in all, this looks like a bigger job than I initially hoped for. So it might take a little longer to investigate and produce a patch...


https://reviews.llvm.org/D38175