[PATCH] D38219: [GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL.

[Igor Breger via Phabricator via llvm-commits]

igorb created this revision.
Herald added subscribers: kristof.beyls, rovka.

Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for shift imm and shift 1, but with shiftCount i8. 
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments has the same type, so for now only shift i8 can use auto generated TableGen patterns.


https://reviews.llvm.org/D38219

Files:
  lib/Target/X86/X86InstructionSelector.cpp
  lib/Target/X86/X86LegalizerInfo.cpp
  lib/Target/X86/X86RegisterBankInfo.cpp
  test/CodeGen/X86/GlobalISel/ashr-scalar.ll
  test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir
  test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir
  test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir
  test/CodeGen/X86/GlobalISel/lshr-scalar.ll
  test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
  test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir
  test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir
  test/CodeGen/X86/GlobalISel/select-shl-scalar.mir
  test/CodeGen/X86/GlobalISel/shl-scalar.ll

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