[llvm] r314071 - [X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Sep 23 22:24:51 2017
New Revision: 314071

URL: http://llvm.org/viewvc/llvm-project?rev=314071&view=rev
Log:
[X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.

Not sure if anything really cares, but this seems like the right thing to do.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=314071&r1=314070&r2=314071&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Sep 23 22:24:51 2017
@@ -7731,7 +7731,9 @@ bool X86InstrInfo::expandPostRAPseudo(Ma
     unsigned SrcReg = MIB->getOperand(0).getReg();
     unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
     MIB->getOperand(0).setReg(XReg);
-    return Expand2AddrUndef(MIB, get(X86::VXORPSrr));
+    Expand2AddrUndef(MIB, get(X86::VXORPSrr));
+    MIB.addReg(SrcReg, RegState::ImplicitDefine);
+    return true;
   }
   case X86::AVX512_128_SET0:
   case X86::AVX512_FsFLD0SS:
@@ -7755,8 +7757,10 @@ bool X86InstrInfo::expandPostRAPseudo(Ma
     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
       MIB->getOperand(0).setReg(XReg);
-      return Expand2AddrUndef(MIB,
-                              get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
+      Expand2AddrUndef(MIB,
+                       get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
+      MIB.addReg(SrcReg, RegState::ImplicitDefine);
+      return true;
     }
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }
@@ -7766,7 +7770,9 @@ bool X86InstrInfo::expandPostRAPseudo(Ma
     if (TRI->getEncodingValue(SrcReg) < 16) {
       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
       MIB->getOperand(0).setReg(XReg);
-      return Expand2AddrUndef(MIB, get(X86::VXORPSrr));
+      Expand2AddrUndef(MIB, get(X86::VXORPSrr));
+      MIB.addReg(SrcReg, RegState::ImplicitDefine);
+      return true;
     }
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }