[llvm] r314062 - [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 23 05:53:03 PDT 2017
Author: nemanjai
Date: Sat Sep 23 05:53:03 2017
New Revision: 314062
URL: http://llvm.org/viewvc/llvm-project?rev=314062&view=rev
Log:
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.
Added:
llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=314062&r1=314061&r2=314062&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Sep 23 05:53:03 2017
@@ -2779,9 +2779,11 @@ SDValue PPCDAGToDAGISel::zeroExtendInput
// - The value has already been zero-extended
// - The value is a positive constant
// - The value comes from a load that isn't a sign-extending load
- // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have
- // to conservatively actually clear the high bits.
- if (Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND)
+ // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext.
+ bool IsTruncateOfZExt = Opc == ISD::TRUNCATE &&
+ (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
+ Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
+ if (Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND || IsTruncateOfZExt)
return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
@@ -3036,6 +3038,21 @@ SDValue PPCDAGToDAGISel::get32BitZExtCom
return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode,
getI32Imm(1, dl)), 0);
}
+ case ISD::SETUGT:
+ // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
+ // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
+ std::swap(LHS, RHS);
+ LLVM_FALLTHROUGH;
+ case ISD::SETULT: {
+ // The upper 32-bits of the register can't be undefined for this sequence.
+ LHS = zeroExtendInputIfNeeded(LHS);
+ RHS = zeroExtendInputIfNeeded(RHS);
+ SDValue Subtract =
+ SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
+ Subtract, getI64Imm(1, dl),
+ getI64Imm(63, dl)), 0);
+ }
}
}
@@ -3176,6 +3193,20 @@ SDValue PPCDAGToDAGISel::get32BitSExtCom
return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift,
getI32Imm(-1, dl)), 0);
}
+ case ISD::SETUGT:
+ // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
+ // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
+ std::swap(LHS, RHS);
+ LLVM_FALLTHROUGH;
+ case ISD::SETULT: {
+ // The upper 32-bits of the register can't be undefined for this sequence.
+ LHS = zeroExtendInputIfNeeded(LHS);
+ RHS = zeroExtendInputIfNeeded(RHS);
+ SDValue Subtract =
+ SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
+ Subtract, getI64Imm(63, dl)), 0);
+ }
}
}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,52 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+%struct.tree_common = type { i8, [3 x i8] }
+declare signext i32 @fn2(...) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
+; CHECK-LABEL: testCompare1:
+; CHECK: # BB#0: # %entry
+; CHECK: lbz r3, 0(r3)
+; CHECK-DAG: clrlwi r3, r3, 31
+; CHECK-DAG: clrldi r3, r3, 32
+; CHECK: lbz r4, 0(r4)
+; CHECK-DAG: clrlwi r4, r4, 31
+; CHECK-DAG: clrldi r4, r4, 32
+; CHECK: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+entry:
+ %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
+ %bf.clear = and i8 %bf.load, 1
+ %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
+ %bf.load1 = load i8, i8* %0, align 4
+ %bf.clear2 = and i8 %bf.load1, 1
+ %cmp = icmp ugt i8 %bf.clear, %bf.clear2
+ %conv = zext i1 %cmp to i32
+ %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
+ ret i32 undef
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: testCompare2:
+; CHECK: # BB#0: # %entry
+; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
+; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
+; CHECK-DAG: clrldi r3, r3, 32
+; CHECK-DAG: clrldi r4, r4, 32
+; CHECK: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %and = and i32 %a, 1
+ %and1 = and i32 %b, 1
+ %cmp = icmp ugt i32 %and, %and1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,52 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+%struct.tree_common = type { i8, [3 x i8] }
+declare signext i32 @fn2(...) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
+; CHECK-LABEL: testCompare1:
+; CHECK: # BB#0: # %entry
+; CHECK: lbz r3, 0(r3)
+; CHECK-DAG: clrlwi r3, r3, 31
+; CHECK-DAG: clrldi r3, r3, 32
+; CHECK: lbz r4, 0(r4)
+; CHECK-DAG: clrlwi r4, r4, 31
+; CHECK-DAG: clrldi r4, r4, 32
+; CHECK: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+entry:
+ %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
+ %bf.clear = and i8 %bf.load, 1
+ %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
+ %bf.load1 = load i8, i8* %0, align 4
+ %bf.clear2 = and i8 %bf.load1, 1
+ %cmp = icmp ult i8 %bf.clear, %bf.clear2
+ %conv = zext i1 %cmp to i32
+ %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
+ ret i32 undef
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: testCompare2:
+; CHECK: # BB#0: # %entry
+; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
+; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
+; CHECK-DAG: clrldi r3, r3, 32
+; CHECK-DAG: clrldi r4, r4, 32
+; CHECK: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %and = and i32 %a, 1
+ %and1 = and i32 %b, 1
+ %cmp = icmp ult i32 %and, %and1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,114 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv2 = zext i1 %cmp to i32
+ ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_sext:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv1 = zext i1 %cmp to i32
+ ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_sext_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv3 = zext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv3 = sext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: stb r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv2 = zext i1 %cmp to i8
+ store i8 %conv2, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_sext_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: neg r3, r3
+; CHECK: stb r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv2 = sext i1 %cmp to i8
+ store i8 %conv2, i8* @glob, align 1
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,115 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_sext:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_sext_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: stw r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_sext_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: neg r3, r3
+; CHECK: stw r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}
+
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,117 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv2 = zext i1 %cmp to i32
+ ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_sext:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv1 = zext i1 %cmp to i32
+ ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_sext_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK: blr
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv3 = zext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK: blr
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv3 = sext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: sth r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv2 = zext i1 %cmp to i16
+ store i16 %conv2, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_sext_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: neg r3, r3
+; CHECK: sth r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv2 = sext i1 %cmp to i16
+ store i16 %conv2, i16* @glob, align 2
+ ret void
+}
+
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv2 = zext i1 %cmp to i32
+ ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_store:
+; CHECK: sub [[REG:r[2-9]+]], r3, r4
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv3 = zext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv3 = sext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_store:
+; CHECK: sub [[REG:r[2-9]+]], r3, r4
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv2 = zext i1 %cmp to i32
+ ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_store:
+; CHECK: sub [[REG:r[2-9]+]], r3, r4
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv3 = zext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv3 = sext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,114 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv3 = zext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_sext:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv3 = sext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_z:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv2 = zext i1 %cmp to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_sext_z:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv2 = sext i1 %cmp to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv3 = zext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ugt i8 %a, %b
+ %conv3 = sext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: stb r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv2 = zext i1 %cmp to i8
+ store i8 %conv2, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_sext_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: neg r3, r3
+; CHECK: stb r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i8 %a, 0
+ %conv2 = sext i1 %cmp to i8
+ store i8 %conv2, i8* @glob, align 1
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,114 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui:
+; CHECK-NOT: clrldi
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_sext:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_sext_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_sext_store:
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: stw r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_sext_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: xori r3, r3, 1
+; CHECK: neg r3, r3
+; CHECK: stw r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,127 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv3 = zext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv3 = sext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv2 = zext i1 %cmp to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv2 = sext i1 %cmp to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv3 = zext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sub [[REG:r[0-9]+]], r4, r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ %conv3 = sext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv2 = zext i1 %cmp to i16
+ store i16 %conv2, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ne i16 %a, 0
+ %conv2 = sext i1 %cmp to i16
+ store i16 %conv2, i16* @glob, align 2
+ ret void
+}
+
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,60 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv3 = zext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv3 = sext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sub [[REG:r[2-9]+]], r3, r4
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv3 = zext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ult i8 %a, %b
+ %conv3 = sext i1 %cmp to i8
+ store i8 %conv3, i8* @glob, align 1
+ ret void
+}
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,108 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui:
+; CHECK: # BB#0: # %entry
+; CHECK-NOT: clrldi
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: blr
+entry:
+ ret i64 0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: blr
+entry:
+ ret i64 0
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NOT: clrldi
+; CHECK: sub [[REG:r[2-9]+]], r3, r4
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NOT: clrldi
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ult i32 %a, %b
+ %sub = sext i1 %cmp to i32
+ store i32 %sub, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK: li [[REG:r[0-9]+]], 0
+; CHECK: stw [[REG]], 0(r3)
+; CHECK-NEXT: blr
+entry:
+ store i32 0, i32* @glob, align 4
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK: li [[REG:r[0-9]+]], 0
+; CHECK: stw [[REG]], 0(r3)
+; CHECK-NEXT: blr
+entry:
+ store i32 0, i32* @glob, align 4
+ ret void
+}
+
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll?rev=314062&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll Sat Sep 23 05:53:03 2017
@@ -0,0 +1,59 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+ at glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv3 = zext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv3 = sext i1 %cmp to i64
+ ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_store:
+; CHECK: sub [[REG:r[2-9]+]], r3, r4
+; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv3 = zext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sub [[REG:r[0-9]+]], r3, r4
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+ %cmp = icmp ult i16 %a, %b
+ %conv3 = sext i1 %cmp to i16
+ store i16 %conv3, i16* @glob, align 2
+ ret void
+}
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