[PATCH] D38181: [x86] swap order of srl (and X, C1), C2 when it saves size

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: lib/Target/X86/X86ISelLowering.cpp:31785
+  // If the mask fits in a byte, then we know we can generate smaller and
+  // potentially better code by shifting first.
+  APInt MaskVal = AndC->getAPIntValue();
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spatel wrote:
> craig.topper wrote:
> > What about a larger than 32-bit and mask that would allow us to use a 32-bit and? Otherwise we use a movabsq to load the immediate.
> Yes, that's a limitation. I'll have to check if that causes regressions for the other patterns. Ok to make that a TODO in this patch?
TODO is fine.


https://reviews.llvm.org/D38181