[PATCH] D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
Herald added subscribers: kristof.beyls, javed.absar, rengolin.

[AArch64] Improve codegen for inverted overflow checking intrinsics.

E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the inverted condition code for the CSEL.

rdar://28495949


Repository:
  rL LLVM

https://reviews.llvm.org/D38160

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-xaluo.ll

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