[llvm] r313941 - [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC).
Eugene Zelenko via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 21 16:20:16 PDT 2017
Author: eugenezelenko
Date: Thu Sep 21 16:20:16 2017
New Revision: 313941
URL: http://llvm.org/viewvc/llvm-project?rev=313941&view=rev
Log:
[CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC).
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/trunk/lib/CodeGen/SpillPlacement.cpp
llvm/trunk/lib/CodeGen/SpillPlacement.h
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=313941&r1=313940&r2=313941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Sep 21 16:20:16 2017
@@ -1,4 +1,4 @@
-//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
+//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,32 +16,64 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/APFloat.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/None.h"
+#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/MemoryLocation.h"
+#include "llvm/CodeGen/DAGCombine.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/Constant.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/Metadata.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <functional>
+#include <iterator>
+#include <string>
+#include <tuple>
+#include <utility>
+#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "dagcombine"
@@ -53,43 +85,41 @@ STATISTIC(OpsNarrowed , "Number of l
STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
STATISTIC(SlicedLoads, "Number of load sliced");
-namespace {
- static cl::opt<bool>
- CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
- cl::desc("Enable DAG combiner's use of IR alias analysis"));
-
- static cl::opt<bool>
- UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
- cl::desc("Enable DAG combiner's use of TBAA"));
+static cl::opt<bool>
+CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
+ cl::desc("Enable DAG combiner's use of IR alias analysis"));
+
+static cl::opt<bool>
+UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
+ cl::desc("Enable DAG combiner's use of TBAA"));
#ifndef NDEBUG
- static cl::opt<std::string>
- CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
- cl::desc("Only use DAG-combiner alias analysis in this"
- " function"));
+static cl::opt<std::string>
+CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
+ cl::desc("Only use DAG-combiner alias analysis in this"
+ " function"));
#endif
- /// Hidden option to stress test load slicing, i.e., when this option
- /// is enabled, load slicing bypasses most of its profitability guards.
- static cl::opt<bool>
- StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
- cl::desc("Bypass the profitability model of load "
- "slicing"),
- cl::init(false));
-
- static cl::opt<bool>
- MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
- cl::desc("DAG combiner may split indexing from loads"));
+/// Hidden option to stress test load slicing, i.e., when this option
+/// is enabled, load slicing bypasses most of its profitability guards.
+static cl::opt<bool>
+StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
+ cl::desc("Bypass the profitability model of load slicing"),
+ cl::init(false));
+
+static cl::opt<bool>
+ MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
+ cl::desc("DAG combiner may split indexing from loads"));
-//------------------------------ DAGCombiner ---------------------------------//
+namespace {
class DAGCombiner {
SelectionDAG &DAG;
const TargetLowering &TLI;
CombineLevel Level;
CodeGenOpt::Level OptLevel;
- bool LegalOperations;
- bool LegalTypes;
+ bool LegalOperations = false;
+ bool LegalTypes = false;
bool ForCodeSize;
/// \brief Worklist of all of the nodes that need to be simplified.
@@ -128,6 +158,19 @@ namespace {
SDValue visit(SDNode *N);
public:
+ DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
+ : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
+ OptLevel(OL), AA(AA) {
+ ForCodeSize = DAG.getMachineFunction().getFunction()->optForSize();
+
+ MaximumLegalStoreInBits = 0;
+ for (MVT VT : MVT::all_valuetypes())
+ if (EVT(VT).isSimple() && VT != MVT::Other &&
+ TLI.isTypeLegal(EVT(VT)) &&
+ VT.getSizeInBits() >= MaximumLegalStoreInBits)
+ MaximumLegalStoreInBits = VT.getSizeInBits();
+ }
+
/// Add to the worklist making sure its instance is at the back (next to be
/// processed.)
void AddToWorklist(SDNode *N) {
@@ -433,12 +476,14 @@ namespace {
/// Holds a pointer to an LSBaseSDNode as well as information on where it
/// is located in a sequence of memory operations connected by a chain.
struct MemOpLink {
- MemOpLink(LSBaseSDNode *N, int64_t Offset)
- : MemNode(N), OffsetFromBase(Offset) {}
// Ptr to the mem node.
LSBaseSDNode *MemNode;
+
// Offset from the base ptr.
int64_t OffsetFromBase;
+
+ MemOpLink(LSBaseSDNode *N, int64_t Offset)
+ : MemNode(N), OffsetFromBase(Offset) {}
};
/// This is a helper function for visitMUL to check the profitability
@@ -449,7 +494,6 @@ namespace {
SDValue &AddNode,
SDValue &ConstNode);
-
/// This is a helper function for visitAND and visitZERO_EXTEND. Returns
/// true if the (and (load x) c) pattern matches an extload. ExtVT returns
/// the type of the loaded value to be extended. LoadedVT returns the type
@@ -501,19 +545,6 @@ namespace {
SDValue distributeTruncateThroughAnd(SDNode *N);
public:
- DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
- : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
- OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(AA) {
- ForCodeSize = DAG.getMachineFunction().getFunction()->optForSize();
-
- MaximumLegalStoreInBits = 0;
- for (MVT VT : MVT::all_valuetypes())
- if (EVT(VT).isSimple() && VT != MVT::Other &&
- TLI.isTypeLegal(EVT(VT)) &&
- VT.getSizeInBits() >= MaximumLegalStoreInBits)
- MaximumLegalStoreInBits = VT.getSizeInBits();
- }
-
/// Runs the dag combiner on all nodes in the work list
void Run(CombineLevel AtLevel);
@@ -542,14 +573,12 @@ namespace {
return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
}
};
-}
-
-namespace {
/// This class is a DAGUpdateListener that removes any deleted
/// nodes from the worklist.
class WorklistRemover : public SelectionDAG::DAGUpdateListener {
DAGCombiner &DC;
+
public:
explicit WorklistRemover(DAGCombiner &dc)
: SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
@@ -558,7 +587,8 @@ public:
DC.removeFromWorklist(N);
}
};
-}
+
+} // end anonymous namespace
//===----------------------------------------------------------------------===//
// TargetLowering::DAGCombinerInfo implementation
@@ -578,7 +608,6 @@ CombineTo(SDNode *N, SDValue Res, bool A
return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
}
-
SDValue TargetLowering::DAGCombinerInfo::
CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
@@ -1683,7 +1712,6 @@ SDValue DAGCombiner::visitTokenFactor(SD
// Check each of the operands.
for (const SDValue &Op : TF->op_values()) {
-
switch (Op.getOpcode()) {
case ISD::EntryToken:
// Entry tokens don't need to be added to the list. They are
@@ -4767,20 +4795,22 @@ SDNode *DAGCombiner::MatchRotate(SDValue
}
namespace {
+
/// Represents known origin of an individual byte in load combine pattern. The
/// value of the byte is either constant zero or comes from memory.
struct ByteProvider {
// For constant zero providers Load is set to nullptr. For memory providers
// Load represents the node which loads the byte from memory.
// ByteOffset is the offset of the byte in the value produced by the load.
- LoadSDNode *Load;
- unsigned ByteOffset;
+ LoadSDNode *Load = nullptr;
+ unsigned ByteOffset = 0;
- ByteProvider() : Load(nullptr), ByteOffset(0) {}
+ ByteProvider() = default;
static ByteProvider getMemory(LoadSDNode *Load, unsigned ByteOffset) {
return ByteProvider(Load, ByteOffset);
}
+
static ByteProvider getConstantZero() { return ByteProvider(nullptr, 0); }
bool isConstantZero() const { return !Load; }
@@ -4795,6 +4825,8 @@ private:
: Load(Load), ByteOffset(ByteOffset) {}
};
+} // end anonymous namespace
+
/// Recursively traverses the expression calculating the origin of the requested
/// byte of the given value. Returns None if the provider can't be calculated.
///
@@ -4806,9 +4838,9 @@ private:
/// Because the parts of the expression are not allowed to have more than one
/// use this function iterates over trees, not DAGs. So it never visits the same
/// node more than once.
-const Optional<ByteProvider> calculateByteProvider(SDValue Op, unsigned Index,
- unsigned Depth,
- bool Root = false) {
+static const Optional<ByteProvider>
+calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth,
+ bool Root = false) {
// Typical i64 by i8 pattern requires recursion up to 8 calls depth
if (Depth == 10)
return None;
@@ -4892,7 +4924,6 @@ const Optional<ByteProvider> calculateBy
return None;
}
-} // namespace
/// Match a pattern where a wide type scalar value is loaded by several narrow
/// loads and combined by shifts and ors. Fold it into a single load or a load
@@ -5005,7 +5036,7 @@ SDValue DAGCombiner::MatchLoadCombine(SD
Loads.insert(L);
}
- assert(Loads.size() > 0 && "All the bytes of the value must be loaded from "
+ assert(!Loads.empty() && "All the bytes of the value must be loaded from "
"memory, so there must be at least one load which produces the value");
assert(Base && "Base address of the accessed memory location must be set");
assert(FirstOffset != INT64_MAX && "First byte offset must be set");
@@ -5732,7 +5763,6 @@ SDValue DAGCombiner::visitSRA(SDNode *N)
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
TLI.isTruncateFree(VT, TruncVT)) {
-
SDLoc DL(N);
SDValue Amt = DAG.getConstant(ShiftAmt, DL,
getShiftAmountTy(N0.getOperand(0).getValueType()));
@@ -5782,7 +5812,6 @@ SDValue DAGCombiner::visitSRA(SDNode *N)
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
-
// If the sign bit is known to be zero, switch this to a SRL.
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
@@ -6106,7 +6135,6 @@ SDValue DAGCombiner::visitCTPOP(SDNode *
return SDValue();
}
-
/// \brief Generate Min/Max node
static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
SDValue RHS, SDValue True, SDValue False,
@@ -6469,7 +6497,6 @@ static SDValue ConvertSelectToConcatVect
}
SDValue DAGCombiner::visitMSCATTER(SDNode *N) {
-
if (Level >= AfterLegalizeTypes)
return SDValue();
@@ -6530,7 +6557,6 @@ SDValue DAGCombiner::visitMSCATTER(SDNod
}
SDValue DAGCombiner::visitMSTORE(SDNode *N) {
-
if (Level >= AfterLegalizeTypes)
return SDValue();
@@ -6545,7 +6571,6 @@ SDValue DAGCombiner::visitMSTORE(SDNode
// prevents the type legalizer from unrolling SETCC into scalar comparisons
// and enables future optimizations (e.g. min/max pattern matching on X86).
if (Mask.getOpcode() == ISD::SETCC) {
-
// Check if any splitting is required.
if (TLI.getTypeAction(*DAG.getContext(), VT) !=
TargetLowering::TypeSplitVector)
@@ -6602,7 +6627,6 @@ SDValue DAGCombiner::visitMSTORE(SDNode
}
SDValue DAGCombiner::visitMGATHER(SDNode *N) {
-
if (Level >= AfterLegalizeTypes)
return SDValue();
@@ -6679,7 +6703,6 @@ SDValue DAGCombiner::visitMGATHER(SDNode
}
SDValue DAGCombiner::visitMLOAD(SDNode *N) {
-
if (Level >= AfterLegalizeTypes)
return SDValue();
@@ -6691,7 +6714,6 @@ SDValue DAGCombiner::visitMLOAD(SDNode *
// SETCC, then split both nodes and its operands before legalization. This
// prevents the type legalizer from unrolling SETCC into scalar comparisons
// and enables future optimizations (e.g. min/max pattern matching on X86).
-
if (Mask.getOpcode() == ISD::SETCC) {
EVT VT = N->getValueType(0);
@@ -8367,7 +8389,6 @@ SDValue DAGCombiner::visitTRUNCATE(SDNod
// we need to be more careful about the vector instructions that we generate.
if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
-
EVT VecTy = N0.getOperand(0).getValueType();
EVT ExTy = N0.getValueType();
EVT TrTy = N->getValueType(0);
@@ -8433,7 +8454,6 @@ SDValue DAGCombiner::visitTRUNCATE(SDNod
N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
N0.getOperand(0).hasOneUse()) {
-
SDValue BuildVect = N0.getOperand(0);
EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
EVT TruncVecEltTy = VT.getVectorElementType();
@@ -10207,8 +10227,8 @@ SDValue DAGCombiner::visitFDIV(SDNode *N
(!LegalOperations ||
// FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
// backend)... we should handle this gracefully after Legalize.
- // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
- TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
+ // TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT) ||
+ TLI.isOperationLegal(ISD::ConstantFP, VT) ||
TLI.isFPImmLegal(Recip, VT)))
return DAG.getNode(ISD::FMUL, DL, VT, N0,
DAG.getConstantFP(Recip, DL, VT), Flags);
@@ -10390,7 +10410,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDN
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
// ...but only if the target supports immediate floating-point values
(!LegalOperations ||
- TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
+ TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT)))
return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
@@ -10408,7 +10428,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDN
if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
!VT.isVector() &&
(!LegalOperations ||
- TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
+ TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) {
SDLoc DL(N);
SDValue Ops[] =
{ N0.getOperand(0), N0.getOperand(1),
@@ -10422,7 +10442,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDN
if (N0.getOpcode() == ISD::ZERO_EXTEND &&
N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
(!LegalOperations ||
- TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
+ TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) {
SDLoc DL(N);
SDValue Ops[] =
{ N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
@@ -10444,7 +10464,7 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDN
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
// ...but only if the target supports immediate floating-point values
(!LegalOperations ||
- TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
+ TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT)))
return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
@@ -10459,10 +10479,9 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDN
// The next optimizations are desirable only if SELECT_CC can be lowered.
if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
// fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
-
if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
(!LegalOperations ||
- TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
+ TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) {
SDLoc DL(N);
SDValue Ops[] =
{ N0.getOperand(0), N0.getOperand(1),
@@ -11571,6 +11590,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N
}
namespace {
+
/// \brief Helper structure used to slice a load in smaller loads.
/// Basically a slice is obtained from the following sequence:
/// Origin = load Ty1, Base
@@ -11588,21 +11608,19 @@ struct LoadedSlice {
struct Cost {
/// Are we optimizing for code size.
bool ForCodeSize;
+
/// Various cost.
- unsigned Loads;
- unsigned Truncates;
- unsigned CrossRegisterBanksCopies;
- unsigned ZExts;
- unsigned Shift;
-
- Cost(bool ForCodeSize = false)
- : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
- CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
+ unsigned Loads = 0;
+ unsigned Truncates = 0;
+ unsigned CrossRegisterBanksCopies = 0;
+ unsigned ZExts = 0;
+ unsigned Shift = 0;
+
+ Cost(bool ForCodeSize = false) : ForCodeSize(ForCodeSize) {}
/// \brief Get the cost of one isolated slice.
Cost(const LoadedSlice &LS, bool ForCodeSize = false)
- : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
- CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
+ : ForCodeSize(ForCodeSize), Loads(1) {
EVT TruncType = LS.Inst->getValueType(0);
EVT LoadedType = LS.getLoadedType();
if (TruncType != LoadedType &&
@@ -11664,13 +11682,17 @@ struct LoadedSlice {
bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
};
+
// The last instruction that represent the slice. This should be a
// truncate instruction.
SDNode *Inst;
+
// The original load instruction.
LoadSDNode *Origin;
+
// The right shift amount in bits from the original load.
unsigned Shift;
+
// The DAG from which Origin came from.
// This is used to get some contextual information about legal types, etc.
SelectionDAG *DAG;
@@ -11872,7 +11894,8 @@ struct LoadedSlice {
return true;
}
};
-}
+
+} // end anonymous namespace
/// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
/// \p UsedBits looks like 0..0 1..1 0..0.
@@ -11930,7 +11953,6 @@ static void adjustCostForPairing(SmallVe
for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
// Set the beginning of the pair.
First = Second) {
-
Second = &LoadedSlices[CurrSlice];
// If First is NULL, it means we start a new pair.
@@ -12061,7 +12083,7 @@ bool DAGCombiner::SliceUpLoad(SDNode *N)
// will be across several bytes. We do not support that.
unsigned Width = User->getValueSizeInBits(0);
if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
- return 0;
+ return false;
// Build the slice for this chain of computations.
LoadedSlice LS(User, LD, Shift, &DAG);
@@ -12186,7 +12208,6 @@ CheckForMaskedLoad(SDValue V, SDValue Pt
return Result;
}
-
/// Check to see if IVal is something that provides a value as specified by
/// MaskInfo. If so, replace the specified store with a narrower store of
/// truncated IVal.
@@ -12247,7 +12268,6 @@ ShrinkLoadReplaceStoreWithStore(const st
.getNode();
}
-
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and
/// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
/// narrowing the load and store if it would end up being a win for performance
@@ -12451,7 +12471,6 @@ bool DAGCombiner::isMulAddWithConstProfi
// Walk all the users of the constant with which we're multiplying.
for (SDNode *Use : ConstNode->uses()) {
-
if (Use == MulNode) // This use is the one we're on right now. Skip it.
continue;
@@ -12750,6 +12769,7 @@ void DAGCombiner::getStoreMergeCandidate
Ptr = BaseIndexOffset::match(Other->getBasePtr(), DAG);
return (BasePtr.equalBaseIndex(Ptr, DAG, Offset));
};
+
// We looking for a root node which is an ancestor to all mergable
// stores. We search up through a load, to our root and then down
// through all children. For instance we will find Store{1,2,3} if
@@ -12796,10 +12816,8 @@ void DAGCombiner::getStoreMergeCandidate
// indirectly through its operand (we already consider dependencies
// through the chain). Check in parallel by searching up from
// non-chain operands of candidates.
-
bool DAGCombiner::checkMergeStoreCandidatesForDependencies(
SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores) {
-
// FIXME: We should be able to truncate a full search of
// predecessors by doing a BFS and keeping tabs the originating
// stores from which worklist nodes come from in a similar way to
@@ -13327,7 +13345,6 @@ bool DAGCombiner::MergeConsecutiveStores
RV = true;
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem);
- continue;
}
return RV;
}
@@ -13578,7 +13595,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *
// prefers, also try this after legalization to catch stores that were created
// by intrinsics or other nodes.
if (!LegalTypes || (TLI.mergeStoresAfterLegalization())) {
- for (;;) {
+ while (true) {
// There can be multiple store sequences on the same chain.
// Keep trying to merge store sequences until we are unable to do so
// or until we merge the last store on the chain.
@@ -14616,7 +14633,7 @@ SDValue DAGCombiner::reduceBuildVecToTru
// If the input is something other than an EXTRACT_VECTOR_ELT with a constant
// index, bail out.
// TODO: Allow undef elements in some cases?
- if (any_of(N->ops(), [VT](SDValue Op) {
+ if (llvm::any_of(N->ops(), [VT](SDValue Op) {
return Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
!isa<ConstantSDNode>(Op.getOperand(1)) ||
Op.getValueType() != VT.getVectorElementType();
@@ -15835,7 +15852,6 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE
if (TLI.isTypeLegal(ScaleVT) &&
0 == (InnerSVT.getSizeInBits() % ScaleSVT.getSizeInBits()) &&
0 == (SVT.getSizeInBits() % ScaleSVT.getSizeInBits())) {
-
int InnerScale = InnerSVT.getSizeInBits() / ScaleSVT.getSizeInBits();
int OuterScale = SVT.getSizeInBits() / ScaleSVT.getSizeInBits();
@@ -16349,7 +16365,6 @@ SDValue DAGCombiner::SimplifySelect(cons
/// the DAG combiner loop to avoid it being looked at.
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
SDValue RHS) {
-
// fold (select (setcc x, [+-]0.0, *lt), NaN, (fsqrt x))
// The select + setcc is redundant, because fsqrt returns NaN for X < 0.
if (const ConstantFPSDNode *NaN = isConstOrConstSplatFP(LHS)) {
@@ -16833,7 +16848,7 @@ SDValue DAGCombiner::BuildSDIV(SDNode *N
if (C->isNullValue())
return SDValue();
- std::vector<SDNode*> Built;
+ std::vector<SDNode *> Built;
SDValue S =
TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
@@ -16879,7 +16894,7 @@ SDValue DAGCombiner::BuildUDIV(SDNode *N
if (C->isNullValue())
return SDValue();
- std::vector<SDNode*> Built;
+ std::vector<SDNode *> Built;
SDValue S =
TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=313941&r1=313940&r2=313941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Sep 21 16:20:16 2017
@@ -1,4 +1,4 @@
-//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
+//===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,22 +11,31 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/APFloat.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
-#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
-#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/Metadata.h"
+#include "llvm/IR/Type.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
@@ -34,14 +43,33 @@
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <tuple>
+#include <utility>
+
using namespace llvm;
#define DEBUG_TYPE "legalizedag"
namespace {
-struct FloatSignAsInt;
+/// Keeps track of state when getting the sign of a floating-point value as an
+/// integer.
+struct FloatSignAsInt {
+ EVT FloatVT;
+ SDValue Chain;
+ SDValue FloatPtr;
+ SDValue IntPtr;
+ MachinePointerInfo IntPointerInfo;
+ MachinePointerInfo FloatPointerInfo;
+ SDValue IntValue;
+ APInt SignMask;
+ uint8_t SignBit;
+};
//===----------------------------------------------------------------------===//
/// This takes an arbitrary SelectionDAG as input and
@@ -54,7 +82,6 @@ struct FloatSignAsInt;
/// as part of its processing. For example, if a target does not support a
/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
/// will attempt merge setcc and brc instructions into brcc's.
-///
class SelectionDAGLegalize {
const TargetMachine &TM;
const TargetLowering &TLI;
@@ -165,11 +192,13 @@ private:
public:
// Node replacement helpers
+
void ReplacedNode(SDNode *N) {
LegalizedNodes.erase(N);
if (UpdatedNodes)
UpdatedNodes->insert(N);
}
+
void ReplaceNode(SDNode *Old, SDNode *New) {
DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
dbgs() << " with: "; New->dump(&DAG));
@@ -182,6 +211,7 @@ public:
UpdatedNodes->insert(New);
ReplacedNode(Old);
}
+
void ReplaceNode(SDValue Old, SDValue New) {
DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
dbgs() << " with: "; New->dump(&DAG));
@@ -191,6 +221,7 @@ public:
UpdatedNodes->insert(New.getNode());
ReplacedNode(Old.getNode());
}
+
void ReplaceNode(SDNode *Old, const SDValue *New) {
DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
@@ -205,7 +236,8 @@ public:
ReplacedNode(Old);
}
};
-}
+
+} // end anonymous namespace
/// Return a vector shuffle operation which
/// performs the same shuffe in terms of order or result bytes, but on a type
@@ -629,13 +661,13 @@ void SelectionDAGLegalize::LegalizeLoadO
}
break;
}
- case TargetLowering::Custom: {
+ case TargetLowering::Custom:
if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
RVal = Res;
RChain = Res.getValue(1);
}
break;
- }
+
case TargetLowering::Promote: {
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
@@ -795,7 +827,7 @@ void SelectionDAGLegalize::LegalizeLoadO
case TargetLowering::Custom:
isCustom = true;
LLVM_FALLTHROUGH;
- case TargetLowering::Legal: {
+ case TargetLowering::Legal:
Value = SDValue(Node, 0);
Chain = SDValue(Node, 1);
@@ -816,8 +848,8 @@ void SelectionDAGLegalize::LegalizeLoadO
}
}
break;
- }
- case TargetLowering::Expand:
+
+ case TargetLowering::Expand: {
EVT DestVT = Node->getValueType(0);
if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
// If the source type is not legal, see if there is a legal extload to
@@ -883,6 +915,7 @@ void SelectionDAGLegalize::LegalizeLoadO
Chain = Result.getValue(1);
break;
}
+ }
}
// Since loads produce two values, make sure to remember that we legalized
@@ -984,11 +1017,10 @@ void SelectionDAGLegalize::LegalizeOp(SD
Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
break;
}
- case ISD::ATOMIC_STORE: {
+ case ISD::ATOMIC_STORE:
Action = TLI.getOperationAction(Node->getOpcode(),
Node->getOperand(2).getValueType());
break;
- }
case ISD::SELECT_CC:
case ISD::SETCC:
case ISD::BR_CC: {
@@ -1092,7 +1124,6 @@ void SelectionDAGLegalize::LegalizeOp(SD
Action = getStrictFPOpcodeAction(TLI, Node->getOpcode(),
Node->getValueType(0));
break;
-
default:
if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
Action = TargetLowering::Legal;
@@ -1143,8 +1174,8 @@ void SelectionDAGLegalize::LegalizeOp(SD
if (SAO != Op2)
NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
}
+ break;
}
- break;
}
if (NewNode != Node) {
@@ -1154,7 +1185,7 @@ void SelectionDAGLegalize::LegalizeOp(SD
switch (Action) {
case TargetLowering::Legal:
return;
- case TargetLowering::Custom: {
+ case TargetLowering::Custom:
// FIXME: The handling for custom lowering with multiple results is
// a complete mess.
if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
@@ -1174,7 +1205,6 @@ void SelectionDAGLegalize::LegalizeOp(SD
return;
}
LLVM_FALLTHROUGH;
- }
case TargetLowering::Expand:
if (ExpandNode(Node))
return;
@@ -1200,13 +1230,11 @@ void SelectionDAGLegalize::LegalizeOp(SD
case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END:
break;
- case ISD::LOAD: {
+ case ISD::LOAD:
return LegalizeLoadOps(Node);
- }
- case ISD::STORE: {
+ case ISD::STORE:
return LegalizeStoreOps(Node);
}
- }
}
SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
@@ -1363,22 +1391,6 @@ SDValue SelectionDAGLegalize::ExpandVect
return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
}
-namespace {
-/// Keeps track of state when getting the sign of a floating-point value as an
-/// integer.
-struct FloatSignAsInt {
- EVT FloatVT;
- SDValue Chain;
- SDValue FloatPtr;
- SDValue IntPtr;
- MachinePointerInfo IntPointerInfo;
- MachinePointerInfo FloatPointerInfo;
- SDValue IntValue;
- APInt SignMask;
- uint8_t SignBit;
-};
-}
-
/// Bitcast a floating-point value to an integer value. Only bitcast the part
/// containing the sign bit if the target has no integer value capable of
/// holding all bits of the floating-point value.
@@ -1755,8 +1767,8 @@ ExpandBVWithShuffles(SDNode *Node, Selec
// We do this in two phases; first to check the legality of the shuffles,
// and next, assuming that all shuffles are legal, to create the new nodes.
for (int Phase = 0; Phase < 2; ++Phase) {
- SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
- NewIntermedVals;
+ SmallVector<std::pair<SDValue, SmallVector<int, 16>>, 16> IntermedVals,
+ NewIntermedVals;
for (unsigned i = 0; i < NumElems; ++i) {
SDValue V = Node->getOperand(i);
if (V.isUndef())
@@ -2500,7 +2512,7 @@ SDValue SelectionDAGLegalize::PromoteLeg
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
- while (1) {
+ while (true) {
NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
assert(NewInTy.isInteger() && "Ran out of possibilities!");
@@ -2541,7 +2553,7 @@ SDValue SelectionDAGLegalize::PromoteLeg
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
- while (1) {
+ while (true) {
NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
assert(NewOutTy.isInteger() && "Ran out of possibilities!");
@@ -2561,7 +2573,6 @@ SDValue SelectionDAGLegalize::PromoteLeg
// Otherwise, try a larger type.
}
-
// Okay, we found the operation and type to use.
SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
@@ -3062,10 +3073,9 @@ bool SelectionDAGLegalize::ExpandNode(SD
case ISD::INSERT_SUBVECTOR:
Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
break;
- case ISD::CONCAT_VECTORS: {
+ case ISD::CONCAT_VECTORS:
Results.push_back(ExpandVectorBuildThroughStack(Node));
break;
- }
case ISD::SCALAR_TO_VECTOR:
Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
break;
@@ -3083,14 +3093,12 @@ bool SelectionDAGLegalize::ExpandNode(SD
SDValue Op0 = Node->getOperand(0);
SDValue Op1 = Node->getOperand(1);
if (!TLI.isTypeLegal(EltVT)) {
-
EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
// BUILD_VECTOR operands are allowed to be wider than the element type.
// But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
// it.
if (NewEltVT.bitsLT(EltVT)) {
-
// Convert shuffle node.
// If original node was v4i64 and the new EltVT is i32,
// cast operands to v8i32 and re-build the mask.
@@ -3457,7 +3465,6 @@ bool SelectionDAGLegalize::ExpandNode(SD
// Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
// Sub:
// Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
- //
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
@@ -4375,7 +4382,7 @@ void SelectionDAGLegalize::PromoteNode(S
case ISD::FREM:
case ISD::FMINNUM:
case ISD::FMAXNUM:
- case ISD::FPOW: {
+ case ISD::FPOW:
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
@@ -4383,8 +4390,7 @@ void SelectionDAGLegalize::PromoteNode(S
Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
Tmp3, DAG.getIntPtrConstant(0, dl)));
break;
- }
- case ISD::FMA: {
+ case ISD::FMA:
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
@@ -4393,7 +4399,6 @@ void SelectionDAGLegalize::PromoteNode(S
DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
DAG.getIntPtrConstant(0, dl)));
break;
- }
case ISD::FCOPYSIGN:
case ISD::FPOWI: {
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
@@ -4425,13 +4430,12 @@ void SelectionDAGLegalize::PromoteNode(S
case ISD::FLOG10:
case ISD::FABS:
case ISD::FEXP:
- case ISD::FEXP2: {
+ case ISD::FEXP2:
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
Tmp2, DAG.getIntPtrConstant(0, dl)));
break;
- }
case ISD::BUILD_VECTOR: {
MVT EltVT = OVT.getVectorElementType();
MVT NewEltVT = NVT.getVectorElementType();
@@ -4608,7 +4612,7 @@ void SelectionDAG::Legalize() {
// nodes with their original operands intact. Legalization can produce
// new nodes which may themselves need to be legalized. Iterate until all
// nodes have been legalized.
- for (;;) {
+ while (true) {
bool AnyLegalized = false;
for (auto NI = allnodes_end(); NI != allnodes_begin();) {
--NI;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=313941&r1=313940&r2=313941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Thu Sep 21 16:20:16 2017
@@ -1,4 +1,4 @@
-//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
+//===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
//
// The LLVM Compiler Infrastructure
//
@@ -27,15 +27,34 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetLowering.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <utility>
+
using namespace llvm;
namespace {
+
class VectorLegalizer {
SelectionDAG& DAG;
const TargetLowering &TLI;
- bool Changed; // Keep track of whether anything changed
+ bool Changed = false; // Keep track of whether anything changed
/// For nodes that are of legal width, and that have more than one use, this
/// map indicates what regularized operand to use. This allows us to avoid
@@ -128,12 +147,15 @@ class VectorLegalizer {
SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
public:
+ VectorLegalizer(SelectionDAG& dag) :
+ DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
+
/// \brief Begin legalizer the vector operations in the DAG.
bool Run();
- VectorLegalizer(SelectionDAG& dag) :
- DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
};
+} // end anonymous namespace
+
bool VectorLegalizer::Run() {
// Before we start legalizing vector nodes, check if there are any vectors.
bool HasVectors = false;
@@ -477,7 +499,7 @@ SDValue VectorLegalizer::PromoteFP_TO_IN
EVT NewVT;
unsigned NewOpc;
- while (1) {
+ while (true) {
NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
@@ -495,7 +517,6 @@ SDValue VectorLegalizer::PromoteFP_TO_IN
return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
}
-
SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
@@ -503,7 +524,6 @@ SDValue VectorLegalizer::ExpandLoad(SDVa
EVT SrcEltVT = SrcVT.getScalarType();
unsigned NumElem = SrcVT.getVectorNumElements();
-
SDValue NewChain;
SDValue Value;
if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
@@ -1117,8 +1137,6 @@ SDValue VectorLegalizer::UnrollVSETCC(SD
return DAG.getBuildVector(VT, dl, Ops);
}
-}
-
bool SelectionDAG::LegalizeVectors() {
return VectorLegalizer(*this).Run();
}
Modified: llvm/trunk/lib/CodeGen/SpillPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SpillPlacement.cpp?rev=313941&r1=313940&r2=313941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SpillPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/SpillPlacement.cpp Thu Sep 21 16:20:16 2017
@@ -1,4 +1,4 @@
-//===-- SpillPlacement.cpp - Optimal Spill Code Placement -----------------===//
+//===- SpillPlacement.cpp - Optimal Spill Code Placement ------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -28,21 +28,31 @@
//===----------------------------------------------------------------------===//
#include "SpillPlacement.h"
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/EdgeBundles.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ManagedStatic.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/BlockFrequency.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <utility>
using namespace llvm;
#define DEBUG_TYPE "spill-code-placement"
char SpillPlacement::ID = 0;
+
+char &llvm::SpillPlacementID = SpillPlacement::ID;
+
INITIALIZE_PASS_BEGIN(SpillPlacement, DEBUG_TYPE,
"Spill Code Placement Analysis", true, true)
INITIALIZE_PASS_DEPENDENCY(EdgeBundles)
@@ -50,8 +60,6 @@ INITIALIZE_PASS_DEPENDENCY(MachineLoopIn
INITIALIZE_PASS_END(SpillPlacement, DEBUG_TYPE,
"Spill Code Placement Analysis", true, true)
-char &llvm::SpillPlacementID = SpillPlacement::ID;
-
void SpillPlacement::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
AU.addRequired<MachineBlockFrequencyInfo>();
@@ -68,10 +76,10 @@ void SpillPlacement::getAnalysisUsage(An
/// The node Value is positive when the variable should be in a register. The
/// value can change when linked nodes change, but convergence is very fast
/// because all weights are positive.
-///
struct SpillPlacement::Node {
/// BiasN - Sum of blocks that prefer a spill.
BlockFrequency BiasN;
+
/// BiasP - Sum of blocks that prefer a register.
BlockFrequency BiasP;
@@ -80,7 +88,7 @@ struct SpillPlacement::Node {
/// variable should go in a register through this bundle.
int Value;
- typedef SmallVector<std::pair<BlockFrequency, unsigned>, 4> LinkVector;
+ using LinkVector = SmallVector<std::pair<BlockFrequency, unsigned>, 4>;
/// Links - (Weight, BundleNo) for all transparent blocks connecting to other
/// bundles. The weights are all positive block frequencies.
@@ -104,7 +112,7 @@ struct SpillPlacement::Node {
}
/// clear - Reset per-query data, but preserve frequencies that only depend on
- // the CFG.
+ /// the CFG.
void clear(const BlockFrequency &Threshold) {
BiasN = BiasP = Value = 0;
SumLinkWeights = Threshold;
@@ -260,14 +268,14 @@ void SpillPlacement::addConstraints(Arra
// Live-in to block?
if (I->Entry != DontCare) {
- unsigned ib = bundles->getBundle(I->Number, 0);
+ unsigned ib = bundles->getBundle(I->Number, false);
activate(ib);
nodes[ib].addBias(Freq, I->Entry);
}
// Live-out from block?
if (I->Exit != DontCare) {
- unsigned ob = bundles->getBundle(I->Number, 1);
+ unsigned ob = bundles->getBundle(I->Number, true);
activate(ob);
nodes[ob].addBias(Freq, I->Exit);
}
@@ -281,8 +289,8 @@ void SpillPlacement::addPrefSpill(ArrayR
BlockFrequency Freq = BlockFrequencies[*I];
if (Strong)
Freq += Freq;
- unsigned ib = bundles->getBundle(*I, 0);
- unsigned ob = bundles->getBundle(*I, 1);
+ unsigned ib = bundles->getBundle(*I, false);
+ unsigned ob = bundles->getBundle(*I, true);
activate(ib);
activate(ob);
nodes[ib].addBias(Freq, PrefSpill);
@@ -294,8 +302,8 @@ void SpillPlacement::addLinks(ArrayRef<u
for (ArrayRef<unsigned>::iterator I = Links.begin(), E = Links.end(); I != E;
++I) {
unsigned Number = *I;
- unsigned ib = bundles->getBundle(Number, 0);
- unsigned ob = bundles->getBundle(Number, 1);
+ unsigned ib = bundles->getBundle(Number, false);
+ unsigned ob = bundles->getBundle(Number, true);
// Ignore self-loops.
if (ib == ob)
Modified: llvm/trunk/lib/CodeGen/SpillPlacement.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SpillPlacement.h?rev=313941&r1=313940&r2=313941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SpillPlacement.h (original)
+++ llvm/trunk/lib/CodeGen/SpillPlacement.h Thu Sep 21 16:20:16 2017
@@ -1,4 +1,4 @@
-//===-- SpillPlacement.h - Optimal Spill Code Placement --------*- C++ -*--===//
+//===- SpillPlacement.h - Optimal Spill Code Placement ---------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
@@ -37,9 +37,9 @@ namespace llvm {
class BitVector;
class EdgeBundles;
-class MachineBasicBlock;
-class MachineLoopInfo;
class MachineBlockFrequencyInfo;
+class MachineFunction;
+class MachineLoopInfo;
class SpillPlacement : public MachineFunctionPass {
struct Node;
@@ -47,7 +47,7 @@ class SpillPlacement : public MachineFun
const EdgeBundles *bundles;
const MachineLoopInfo *loops;
const MachineBlockFrequencyInfo *MBFI;
- Node *nodes;
+ Node *nodes = nullptr;
// Nodes that are active in the current computation. Owned by the prepare()
// caller.
@@ -73,7 +73,7 @@ class SpillPlacement : public MachineFun
public:
static char ID; // Pass identification, replacement for typeid.
- SpillPlacement() : MachineFunctionPass(ID), nodes(nullptr) {}
+ SpillPlacement() : MachineFunctionPass(ID) {}
~SpillPlacement() override { releaseMemory(); }
/// BorderConstraint - A basic block has separate constraints for entry and
@@ -155,16 +155,16 @@ public:
}
private:
- bool runOnMachineFunction(MachineFunction&) override;
- void getAnalysisUsage(AnalysisUsage&) const override;
+ bool runOnMachineFunction(MachineFunction &mf) override;
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
void releaseMemory() override;
- void activate(unsigned);
+ void activate(unsigned n);
void setThreshold(const BlockFrequency &Entry);
- bool update(unsigned);
+ bool update(unsigned n);
};
} // end namespace llvm
-#endif
+#endif // LLVM_LIB_CODEGEN_SPILLPLACEMENT_H
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=313941&r1=313940&r2=313941&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Thu Sep 21 16:20:16 2017
@@ -1,4 +1,4 @@
-//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
+//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
//
// The LLVM Compiler Infrastructure
//
@@ -13,32 +13,55 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/Analysis.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/StackMaps.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
-#include "llvm/IR/Mangler.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
#include "llvm/Support/BranchProbability.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
-#include <cctype>
+#include <algorithm>
+#include <cassert>
+#include <cstring>
+#include <cstddef>
+#include <cstdint>
+#include <iterator>
+#include <string>
+#include <tuple>
+#include <utility>
+
using namespace llvm;
static cl::opt<bool> JumpIsExpensiveOverride(
@@ -78,7 +101,6 @@ static cl::opt<int> MinPercentageForPred
cl::Hidden);
/// InitLibcallNames - Set default libcall names.
-///
static void InitLibcallNames(const char **Names, const Triple &TT) {
#define HANDLE_LIBCALL(code, name) \
Names[RTLIB::code] = name;
@@ -428,7 +450,6 @@ RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_
}
/// InitCmpLibcallCCs - Set default comparison libcall CC.
-///
static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
@@ -614,7 +635,6 @@ void TargetLoweringBase::initActions() {
// On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
// here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
- //
setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
}
@@ -726,7 +746,7 @@ TargetLoweringBase::getTypeConversion(LL
// found, fallback to the usual mechanism of widening/splitting the
// vector.
EVT OldEltVT = EltVT;
- while (1) {
+ while (true) {
// Increase the bitwidth of the element to the next pow-of-two
// (which is greater than 8 bits).
EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
@@ -754,7 +774,7 @@ TargetLoweringBase::getTypeConversion(LL
// Try to widen the vector until a legal type is found.
// If there is no wider legal type, split the vector.
- while (1) {
+ while (true) {
// Round up to the next power of 2.
NumElts = (unsigned)NextPowerOf2(NumElts);
@@ -1065,7 +1085,7 @@ void TargetLoweringBase::computeRegister
bool IsLegalWiderType = false;
LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
switch (PreferredAction) {
- case TypePromoteInteger: {
+ case TypePromoteInteger:
// Try to promote the elements of integer vectors. If no legal
// promotion was found, fall through to the widen-vector method.
for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
@@ -1085,8 +1105,8 @@ void TargetLoweringBase::computeRegister
if (IsLegalWiderType)
break;
LLVM_FALLTHROUGH;
- }
- case TypeWidenVector: {
+
+ case TypeWidenVector:
// Try to widen the vector.
for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
MVT SVT = (MVT::SimpleValueType) nVT;
@@ -1103,7 +1123,7 @@ void TargetLoweringBase::computeRegister
if (IsLegalWiderType)
break;
LLVM_FALLTHROUGH;
- }
+
case TypeSplitVector:
case TypeScalarizeVector: {
MVT IntermediateVT;
@@ -1168,7 +1188,6 @@ MVT::SimpleValueType TargetLoweringBase:
/// This method returns the number of registers needed, and the VT for each
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
-///
unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
EVT &IntermediateVT,
unsigned &NumIntermediates,
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