[PATCH] D38120: [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.

For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.

I believe this supercedes https://reviews.llvm.org/D38025 which was trying to switch the register&register form back to pre-PR22995.


https://reviews.llvm.org/D38120

Files:
  lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  lib/Target/X86/X86InstrArithmetic.td
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86MacroFusion.cpp
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  test/CodeGen/X86/absolute-bit-mask.ll
  test/CodeGen/X86/post-ra-sched-with-debug.mir
  test/CodeGen/X86/testl-commute.ll
  test/MC/Disassembler/X86/x86-16.txt
  test/MC/X86/intel-syntax.s
  test/MC/X86/x86-16.s
  test/MC/X86/x86-32.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D38120.116140.patch
Type: text/x-patch
Size: 13347 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170921/d59103b9/attachment.bin>