[PATCH] D38103: AMDGPU: Fix crash on immediate operand

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

We can have a v_mac with an immediate src0.
We can still fold if it's an inline immediate,
 otherwise it already uses the constant bus.


https://reviews.llvm.org/D38103

Files:
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  test/CodeGen/AMDGPU/twoaddr-mad.mir


Index: test/CodeGen/AMDGPU/twoaddr-mad.mir
===================================================================
--- test/CodeGen/AMDGPU/twoaddr-mad.mir
+++ test/CodeGen/AMDGPU/twoaddr-mad.mir
@@ -130,3 +130,40 @@
     %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit %exec
 
 ...
+
+# This can still fold if this is an inline immediate.
+
+# GCN-LABEL: name: test_madak_inlineimm_src0_f32
+# GCN: %1 = V_MADMK_F32 1073741824, 1078523331, %2, implicit %exec
+
+---
+name:            test_madak_inlineimm_src0_f32
+registers:
+  - { id: 0, class: vgpr_32}
+  - { id: 1, class: vgpr_32 }
+  - { id: 2, class: vgpr_32 }
+body:             |
+  bb.0:
+
+    %0 = V_MOV_B32_e32 1078523331, implicit %exec
+    %1 = V_MAC_F32_e32 1073741824, %0, %2, implicit %exec
+
+...
+# Non-inline immediate uses constant bus already.
+
+# GCN-LABEL: name: test_madak_otherimm_src0_f32
+# GCN: %1 = V_MAC_F32_e32 1120403456, %0, %1, implicit %exec
+
+---
+name:            test_madak_otherimm_src0_f32
+registers:
+  - { id: 0, class: vgpr_32}
+  - { id: 1, class: vgpr_32 }
+  - { id: 2, class: vgpr_32 }
+body:             |
+  bb.0:
+
+    %0 = V_MOV_B32_e32 1078523331, implicit %exec
+    %1 = V_MAC_F32_e32 1120403456, %0, %2, implicit %exec
+
+...
Index: lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.h
+++ lib/Target/AMDGPU/SIInstrInfo.h
@@ -663,6 +663,12 @@
                        const MachineOperand &MO,
                        const MCOperandInfo &OpInfo) const;
 
+  bool usesConstantBus(const MachineRegisterInfo &MRI,
+                       const MachineInstr &MI,
+                       const MachineOperand &MO) const {
+    return usesConstantBus(MRI, MO, MI.getDesc().OpInfo[MI.getOperandNo(&MO)]);
+  }
+
   /// \brief Return true if this instruction has any modifiers.
   ///  e.g. src[012]_mod, omod, clamp.
   bool hasModifiers(unsigned Opcode) const;
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2193,7 +2193,7 @@
 
   if (!Src0Mods && !Src1Mods && !Clamp && !Omod &&
       // If we have an SGPR input, we will violate the constant bus restriction.
-      !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg())) {
+      !usesConstantBus(MBB->getParent()->getRegInfo(), MI, *Src0)) {
     if (auto Imm = getFoldableImm(Src2)) {
       return BuildMI(*MBB, MI, MI.getDebugLoc(),
                      get(IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32))


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