[llvm] r313613 - [X86][Skylake] Adding the scheduling information for the SkylakeClient target

[Gadi Haber via llvm-commits]

Author: gadi.haber
Date: Mon Sep 18 23:19:27 2017
New Revision: 313613

URL: http://llvm.org/viewvc/llvm-project?rev=313613&view=rev
Log:
[X86][Skylake] Adding the scheduling information for the SkylakeClient target

This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target.
We used the scheduling information retrieved from the Skylake architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction.
The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879.

Please expect some performance fluctuations due to code alignment effects.

Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena
Differential Revision: https://reviews.llvm.org/D37294

Added:
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td   (with props)
Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86Schedule.td
    llvm/trunk/test/CodeGen/X86/aes-schedule.ll
    llvm/trunk/test/CodeGen/X86/avx-schedule.ll
    llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
    llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll
    llvm/trunk/test/CodeGen/X86/f16c-schedule.ll
    llvm/trunk/test/CodeGen/X86/fma-schedule.ll
    llvm/trunk/test/CodeGen/X86/recip-fastmath.ll
    llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll
    llvm/trunk/test/CodeGen/X86/sse-schedule.ll
    llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
    llvm/trunk/test/CodeGen/X86/sse3-schedule.ll
    llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
    llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
    llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Mon Sep 18 23:19:27 2017
@@ -602,8 +602,7 @@ def SKLFeatures : ProcessorFeatures<BDWF
   FeatureFastVectorFSQRT
 ]>;
 
-// FIXME: define SKL model
-class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
+class SkylakeClientProc<string Name> : ProcModel<Name, SkylakeClientModel,
                                                  SKLFeatures.Value, [
     ProcIntelSKL
   ]>;
@@ -641,7 +640,7 @@ def SKXFeatures : ProcessorFeatures<SKLF
 ]>;
 
 // FIXME: define SKX model
-class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
+class SkylakeServerProc<string Name> : ProcModel<Name, SkylakeClientModel,
                                                  SKXFeatures.Value, [
     ProcIntelSKX
   ]>;

Added: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=313613&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (added)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Sep 18 23:19:27 2017
@@ -0,0 +1,4011 @@
+//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for Skylake Client to support
+// instruction scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+def SkylakeClientModel : SchedMachineModel {
+  // All x86 instructions are modeled as a single micro-op, and SKylake can
+  // decode 6 instructions per cycle.
+  let IssueWidth = 6;
+  let MicroOpBufferSize = 224; // Based on the reorder buffer.
+  let LoadLatency = 5;
+  let MispredictPenalty = 14;
+  
+  // Based on the LSD (loop-stream detector) queue size and benchmarking data.
+  let LoopMicroOpBufferSize = 50;
+
+  // This flag is set to allow the scheduler to assign a default model to
+  // unrecognized opcodes.
+  let CompleteModel = 0;
+}
+
+let SchedModel = SkylakeClientModel in {
+
+// Skylake Client can issue micro-ops to 8 different ports in one cycle.
+
+// Ports 0, 1, 5, and 6 handle all computation.
+// Port 4 gets the data half of stores. Store data can be available later than
+// the store address, but since we don't model the latency of stores, we can
+// ignore that.
+// Ports 2 and 3 are identical. They handle loads and the address half of
+// stores. Port 7 can handle address calculations.
+def SKLPort0 : ProcResource<1>;
+def SKLPort1 : ProcResource<1>;
+def SKLPort2 : ProcResource<1>;
+def SKLPort3 : ProcResource<1>;
+def SKLPort4 : ProcResource<1>;
+def SKLPort5 : ProcResource<1>;
+def SKLPort6 : ProcResource<1>;
+def SKLPort7 : ProcResource<1>;
+
+// Many micro-ops are capable of issuing on multiple ports.
+def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
+def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
+def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
+def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
+def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
+def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
+def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
+def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
+def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
+def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
+def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
+def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
+
+// 60 Entry Unified Scheduler
+def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
+                              SKLPort5, SKLPort6, SKLPort7]> {
+  let BufferSize=60;
+}
+
+// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
+// cycles after the memory operand.
+def : ReadAdvance<ReadAfterLd, 5>;
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when queued in the reservation station.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
+                          ProcResourceKind ExePort,
+                          int Lat> {
+  // Register variant is using a single cycle on ExePort.
+  def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
+
+  // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
+  // latency.
+  def : WriteRes<SchedRW.Folded, [SKLPort23, ExePort]> {
+     let Latency = !add(Lat, 5);
+  }
+}
+
+// A folded store needs a cycle on port 4 for the store data, but it does not
+// need an extra port 2/3 cycle to recompute the address.
+def : WriteRes<WriteRMW, [SKLPort4]>;
+
+// Arithmetic.
+defm : SKLWriteResPair<WriteALU,   SKLPort0156, 1>; // Simple integer ALU op.
+defm : SKLWriteResPair<WriteIMul,  SKLPort1,   3>; // Integer multiplication.
+def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
+def SKLDivider : ProcResource<1>; // Integer division issued on port 0.     
+def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.
+  let Latency = 25;
+  let ResourceCycles = [1, 10];
+}
+def : WriteRes<WriteIDivLd, [SKLPort23, SKLPort0, SKLDivider]> {
+  let Latency = 29;
+  let ResourceCycles = [1, 1, 10];
+}
+
+def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
+
+// Integer shifts and rotates.
+defm : SKLWriteResPair<WriteShift, SKLPort06,  1>;
+
+// Loads, stores, and moves, not folded with other operations.
+def : WriteRes<WriteLoad,  [SKLPort23]> { let Latency = 5; }
+def : WriteRes<WriteStore, [SKLPort237, SKLPort4]>;
+def : WriteRes<WriteMove,  [SKLPort0156]>;
+
+// Idioms that clear a register, like xorps %xmm0, %xmm0.
+// These can often bypass execution ports completely.
+def : WriteRes<WriteZero,  []>;
+
+// Branches don't produce values, so they have no latency, but they still
+// consume resources. Indirect branches can fold loads.
+defm : SKLWriteResPair<WriteJump,  SKLPort06,   1>;
+
+// Floating point. This covers both scalar and vector operations.
+defm : SKLWriteResPair<WriteFAdd,   SKLPort1, 3>; // Floating point add/sub/compare.
+defm : SKLWriteResPair<WriteFMul,   SKLPort0, 5>; // Floating point multiplication.
+defm : SKLWriteResPair<WriteFDiv,   SKLPort0, 12>; // 10-14 cycles. // Floating point division.
+defm : SKLWriteResPair<WriteFSqrt,  SKLPort0, 15>; // Floating point square root.
+defm : SKLWriteResPair<WriteFRcp,   SKLPort0, 5>; // Floating point reciprocal estimate.
+defm : SKLWriteResPair<WriteFRsqrt, SKLPort0, 5>; // Floating point reciprocal square root estimate.
+// defm WriteFMA    : X86SchedWritePair; // Fused Multiply Add.
+defm : SKLWriteResPair<WriteFShuffle,  SKLPort5,  1>; // Floating point vector shuffles.
+defm : SKLWriteResPair<WriteFBlend,  SKLPort015,  1>; // Floating point vector blends.
+def : WriteRes<WriteFVarBlend, [SKLPort5]> { // Fp vector variable blends.	       
+  let Latency = 2;
+  let ResourceCycles = [2];
+} 
+def : WriteRes<WriteFVarBlendLd, [SKLPort5, SKLPort23]> {
+  let Latency = 6;
+  let ResourceCycles = [2, 1];
+}
+
+// FMA Scheduling helper class.
+// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
+
+// Vector integer operations.
+defm : SKLWriteResPair<WriteVecALU,   SKLPort15,  1>; // Vector integer ALU op, no logicals.
+defm : SKLWriteResPair<WriteVecShift, SKLPort0,  1>; // Vector integer shifts.
+defm : SKLWriteResPair<WriteVecIMul,  SKLPort0,   5>; // Vector integer multiply.
+defm : SKLWriteResPair<WriteShuffle,  SKLPort5,  1>; // Vector shuffles.
+defm : SKLWriteResPair<WriteBlend,  SKLPort15,  1>; // Vector blends.
+
+def : WriteRes<WriteVarBlend, [SKLPort5]> { // Vector variable blends.
+  let Latency = 2;
+  let ResourceCycles = [2];
+}
+def : WriteRes<WriteVarBlendLd, [SKLPort5, SKLPort23]> {
+  let Latency = 6;
+  let ResourceCycles = [2, 1];
+}
+
+def : WriteRes<WriteMPSAD, [SKLPort0, SKLPort5]> { // Vector MPSAD.     
+  let Latency = 6;
+  let ResourceCycles = [1, 2];
+}
+def : WriteRes<WriteMPSADLd, [SKLPort23, SKLPort0, SKLPort5]> {
+  let Latency = 6;
+  let ResourceCycles = [1, 1, 2];
+}
+
+// Vector bitwise operations.
+// These are often used on both floating point and integer vectors.
+defm : SKLWriteResPair<WriteVecLogic, SKLPort015, 1>; // Vector and/or/xor.
+
+// Conversion between integer and float.
+defm : SKLWriteResPair<WriteCvtF2I, SKLPort1, 3>; // Float -> Integer.
+defm : SKLWriteResPair<WriteCvtI2F, SKLPort1, 4>; // Integer -> Float.
+defm : SKLWriteResPair<WriteCvtF2F, SKLPort1, 3>; // Float -> Float size conversion.
+
+// Strings instructions.
+// Packed Compare Implicit Length Strings, Return Mask
+// String instructions.
+def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
+  let Latency = 10;
+  let ResourceCycles = [3];
+}
+def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
+  let Latency = 10;
+  let ResourceCycles = [3, 1];
+} 
+// Packed Compare Explicit Length Strings, Return Mask
+def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort16, SKLPort5]> {
+  let Latency = 10;
+  let ResourceCycles = [3, 2, 4];
+}
+def : WriteRes<WritePCmpEStrMLd, [SKLPort05, SKLPort16, SKLPort23]> {
+  let Latency = 10;
+  let ResourceCycles = [6, 2, 1];
+} 
+  // Packed Compare Implicit Length Strings, Return Index
+def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
+  let Latency = 11;
+  let ResourceCycles = [3];
+}
+def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
+  let Latency = 11;
+  let ResourceCycles = [3, 1];
+}     
+// Packed Compare Explicit Length Strings, Return Index
+def : WriteRes<WritePCmpEStrI, [SKLPort05, SKLPort16]> {
+  let Latency = 11;
+  let ResourceCycles = [6, 2];
+}
+def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort16, SKLPort5, SKLPort23]> {
+  let Latency = 11;
+  let ResourceCycles = [3, 2, 2, 1];
+}
+
+// AES instructions.
+def : WriteRes<WriteAESDecEnc, [SKLPort5]> { // Decryption, encryption.
+  let Latency = 7;
+  let ResourceCycles = [1];
+}
+def : WriteRes<WriteAESDecEncLd, [SKLPort5, SKLPort23]> {
+  let Latency = 7;
+  let ResourceCycles = [1, 1];
+}
+def : WriteRes<WriteAESIMC, [SKLPort5]> { // InvMixColumn.
+  let Latency = 14;
+  let ResourceCycles = [2];
+}
+def : WriteRes<WriteAESIMCLd, [SKLPort5, SKLPort23]> {
+  let Latency = 14;
+  let ResourceCycles = [2, 1];
+}
+def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5]> { // Key Generation.
+  let Latency = 10;
+  let ResourceCycles = [2, 8];
+}
+def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23]> {
+  let Latency = 10;
+  let ResourceCycles = [2, 7, 1];
+}
+
+// Carry-less multiplication instructions.
+def : WriteRes<WriteCLMul, [SKLPort0, SKLPort5]> {
+  let Latency = 7;
+  let ResourceCycles = [2, 1];
+}
+def : WriteRes<WriteCLMulLd, [SKLPort0, SKLPort5, SKLPort23]> {
+  let Latency = 7;
+  let ResourceCycles = [2, 1, 1];
+}
+
+// Catch-all for expensive system instructions.
+def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
+
+// AVX2.
+defm : SKLWriteResPair<WriteFShuffle256,  SKLPort5,  3>; // Fp 256-bit width vector shuffles.
+defm : SKLWriteResPair<WriteShuffle256,  SKLPort5,  3>;  // 256-bit width vector shuffles.
+def : WriteRes<WriteVarVecShift, [SKLPort0, SKLPort5]> { // Variable vector shifts.
+  let Latency = 2;
+  let ResourceCycles = [2, 1];
+}
+def : WriteRes<WriteVarVecShiftLd, [SKLPort0, SKLPort5, SKLPort23]> {
+  let Latency = 6;
+  let ResourceCycles = [2, 1, 1];
+}
+
+// Old microcoded instructions that nobody use.
+def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
+
+// Fence instructions.
+def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
+
+// Nop, not very useful expect it provides a model for nops!
+def : WriteRes<WriteNop, []>;
+
+////////////////////////////////////////////////////////////////////////////////
+// Horizontal add/sub  instructions.
+////////////////////////////////////////////////////////////////////////////////
+// HADD, HSUB PS/PD
+// x,x / v,v,v.
+def : WriteRes<WriteFHAdd, [SKLPort1]> {
+  let Latency = 3;
+}
+
+// x,m / v,v,m.
+def : WriteRes<WriteFHAddLd, [SKLPort1, SKLPort23]> {
+  let Latency = 7;
+  let ResourceCycles = [1, 1];
+}
+
+// PHADD|PHSUB (S) W/D.
+// v <- v,v.
+def : WriteRes<WritePHAdd, [SKLPort15]>;
+
+// v <- v,m.
+def : WriteRes<WritePHAddLd, [SKLPort15, SKLPort23]> {
+  let Latency = 5;
+  let ResourceCycles = [1, 1];
+}
+
+// Remaining instrs.
+
+def SKLWriteResGroup0 : SchedWriteRes<[SKLPort23]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup0], (instregex "LDDQUrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "LD_F32m")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "LD_F64m")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "LD_F80m")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64from64rm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64rm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64to64rm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVQ64rm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOV(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOV64toPQIrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOV8rm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVAPDrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVAPSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVDDUPrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVDI2PDIrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVDQArm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVDQUrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVNTDQArm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVSHDUPrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVSLDUPrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVSSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm16")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm32")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm8")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVUPDrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVUPSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVZX(16|32|64)rm16")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "MOVZX(16|32|64)rm8")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHNTA")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT0")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT1")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT2")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTF128")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTI128")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSDYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSSYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VLDDQUYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VLDDQUrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOV64toPQIrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPDYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPDrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPSYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDDUPYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDDUPrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDI2PDIrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQAYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQArm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQUYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQUrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVNTDQAYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVNTDQArm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVQI2PQIrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSDrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSHDUPYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSHDUPrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSLDUPYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSLDUPrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPDYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPDrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPSYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPSrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTDYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTDrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTQYrm")>;
+def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTQrm")>;
+
+def SKLWriteResGroup1 : SchedWriteRes<[SKLPort4,SKLPort237]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup1], (instregex "FBSTPm")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVD64mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVNTQmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVQ64mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOV(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOV8mi")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOV8mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVAPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVAPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVDQAmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVDQUmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVHPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVHPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVLPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVLPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTDQmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTI_64mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTImr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVPDI2DImr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVPQI2QImr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVPQIto64mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVSSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVUPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MOVUPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP32m")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP64m")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP80m")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VEXTRACTF128mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VEXTRACTI128mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPDYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPSYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQAYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQAmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQUYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQUmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVHPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVHPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVLPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVLPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTDQYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTDQmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPDYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPSYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPDI2DImr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPQI2QImr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPQIto64mr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVSDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVSSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPDYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPDmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPSYmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPSmr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "VMPTRSTm")>;
+
+def SKLWriteResGroup2 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDSBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDSWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDUSBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDUSWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PAVGBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PAVGWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQDirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTDirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMAXSWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMAXUBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMINSWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMINUBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLDri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLDrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLQri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLQrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLWri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLWrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRADri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRADrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRAWri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRAWrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLDri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLDrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLQri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLQrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLWri")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLWrr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBSBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBSWirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBUSBirr")>;
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBUSWirr")>;
+
+def SKLWriteResGroup3 : SchedWriteRes<[SKLPort1]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PABSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PABSDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PABSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PADDSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PADDSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PADDUSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PADDUSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PAVGBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PAVGWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMINSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMINSDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMINSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMINUBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMINUDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMINUWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNBrr128")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNDrr128")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNWrr128")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSLLDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSLLQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSLLWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRADri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRAWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRLDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRLQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRLWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSUBSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSUBUSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSUBUSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPABSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPABSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPABSDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPABSDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPABSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPABSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNBYrr256")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNBrr128")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNDYrr256")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNDrr128")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNWYrr256")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNWrr128")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLQYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLWYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRADYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRADri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAVDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAVDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAWYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLQYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLWYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSWrr")>;
+
+def SKLWriteResGroup4 : SchedWriteRes<[SKLPort5]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup4], (instregex "COMP_FST0r")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "COM_FST0r")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "FINCSTP")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "FNOP")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "INSERTPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVD64rr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVQ64rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSBrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSDrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDBirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDDirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDQirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDWirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PANDNirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PANDirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PORirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSHUFWri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNBrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNDrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBBirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBDirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBQirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBWirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PXORirr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOV64toPQIrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVDDUPrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVDI2PDIrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVHLPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVLHPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVSDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVSHDUPrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVSLDUPrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVUPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "MOVUPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PACKSSDWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PACKSSWBrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PACKUSDWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PACKUSWBrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PALIGNRrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PBLENDWrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXWQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXWQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFBrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFDri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFHWri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFLWri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PSLLDQri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PSRLDQri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHQDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLQDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "SHUFPDrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "SHUFPSrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "UCOM_FPr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "UCOM_Fr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKHPDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKHPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKLPDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKLPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VBROADCASTSSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VINSERTPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOV64toPQIrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDDUPYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDDUPrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDI2PDIrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVHLPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVLHPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSHDUPYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSHDUPrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSLDUPYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSLDUPrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPDYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPSYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSDWYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSDWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSWBYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSWBrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSDWYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSDWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSWBYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSWBrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPALIGNRYrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPALIGNRrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPBLENDWYrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPBLENDWrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPBROADCASTDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPBROADCASTQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXWQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXWQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFBYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFBrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFDYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFDri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFHWYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFHWri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFLWYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFLWri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSLLDQYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSLLDQri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSRLDQYri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPSRLDQri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHQDQYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLBWYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLBWrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLWDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPDYrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPDrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPSYrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPSrri")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPDYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPSYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPSrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPDYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPDrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPSYrr")>;
+def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPSrr")>;
+
+def SKLWriteResGroup5 : SchedWriteRes<[SKLPort6]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup5], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "ADC(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "ADC8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "ADCX32rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "ADCX64rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "ADOX32rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "ADOX64rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BT(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BTC(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BTC(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BTR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BTR(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BTS(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "BTS(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CDQ")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CLAC")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVAE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVB(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVG(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVGE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVL(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVLE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNO(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNP(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNS(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVO(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVP(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CMOVS(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "CQO")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JAE_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JAE_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JA_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JA_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JBE_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JBE_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JB_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JB_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JE_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JE_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JGE_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JGE_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JG_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JG_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JLE_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JLE_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JL_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JL_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JMP(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JMP_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JMP_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNE_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNE_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNO_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNO_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNP_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNP_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNS_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JNS_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JO_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JO_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JP_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JP_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JS_1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "JS_4")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "RORX32ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "RORX64ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SAR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SAR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SAR8r1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SAR8ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SARX32rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SARX64rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SBB(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SBB8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETAEr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETBr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETEr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETGEr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETGr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETLEr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETLr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETNEr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETNOr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETNPr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETNSr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETOr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETPr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SETSr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHL(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHL(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHL8r1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHL8ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHLX32rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHLX64rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHR8r1")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHR8ri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHRX32rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "SHRX64rr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "STAC")>;
+
+def SKLWriteResGroup6 : SchedWriteRes<[SKLPort15]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup6], (instregex "ANDN32rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ANDN64rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ANDNPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ANDNPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ANDPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ANDPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLENDPDrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLENDPSrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLSI32rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLSI64rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLSMSK32rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLSMSK64rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLSR32rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BLSR64rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BZHI32rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "BZHI64rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MOVAPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MOVAPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MOVDQArr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MOVDQUrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MOVPQI2QIrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MOVSSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ORPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "ORPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PADDBrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PADDDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PADDQrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PADDWrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PANDNrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PANDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PORrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PSUBBrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PSUBDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PSUBQrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PSUBWrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "PXORrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPSYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDPDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDPSYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VANDPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPDYrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPDrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPSYrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPSrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPDYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPSYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQAYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQArr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQUYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQUrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVSSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VORPDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VORPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VORPSYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VORPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDBYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDBrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDQYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDQrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDWYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPADDWrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPANDNYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPANDNrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPANDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPANDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPBLENDDYrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPBLENDDrri")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPORYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPORrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBBYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBBrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBQYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBQrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBWYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBWrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPXORYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VPXORrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VXORPDYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VXORPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VXORPSYrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "VXORPSrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "XORPDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "XORPSrr")>;
+
+def SKLWriteResGroup7 : SchedWriteRes<[SKLPort0156]> {
+  let Latency = 1;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup7], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADD(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADD8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADD8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADD8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "AND(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "AND8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "AND8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "AND8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CBW")>;
+//def: InstRW<[SKLWriteResGroup7], (instregex "CDQE")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CLC")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMC")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMP(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMP8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMP8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMP8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CWDE")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "DEC(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "DEC8r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "INC(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "INC8r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "LAHF")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOV(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOV8ri(_alt?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOV8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr16")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr32")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOVZX(16|32|64)rr16")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "MOVZX(16|32|64)rr8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "NEG(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "NEG8r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "NOOP")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "NOT(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "NOT8r")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "OR(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "OR8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "OR8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "OR8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SAHF")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SGDT64m")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SIDT64m")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SLDT64m")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SMSW16m")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "STC")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "STRm")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SUB(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SUB8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SUB8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SUB8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SYSCALL")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "TEST(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "TEST8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "TEST8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "TEST8rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "XCHG(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "XOR(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "XOR8i8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "XOR8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "XOR8rr(_REV?)")>;
+
+def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDSBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDSWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDUSBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDUSWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PAVGBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PAVGWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQDirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTDirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMAXSWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMAXUBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMINSWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMINUBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLDrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLQrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLWrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRADrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRAWrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLDrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLQrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLWrm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBSBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBSWirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBUSBirm")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBUSWirm")>;
+
+def SKLWriteResGroup13 : SchedWriteRes<[SKLPort0,SKLPort237]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MASKMOVQ64")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVDQU")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPDYmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPDmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPSYmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPSmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVDYmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVDmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVQYmr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVQmr")>;
+
+def SKLWriteResGroup14 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup14], (instregex "FCOM32m")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "FCOM64m")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "FCOMP32m")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "FCOMP64m")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "INSERTPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PALIGNR64irm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PINSRWirmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PSHUFBrm64")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PSHUFWmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHBWirm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHDQirm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHWDirm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLBWirm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLDQirm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLWDirm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MOVHPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MOVHPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MOVLPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MOVLPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PACKSSDWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PACKSSWBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PACKUSDWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PACKUSWBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PALIGNRrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PBLENDWrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PINSRBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PINSRDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PINSRQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PINSRWrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXWQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXWQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFDmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFHWmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFLWmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHQDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLQDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "SHUFPDrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "SHUFPSrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKHPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKHPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKLPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKLPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VINSERTPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VMOVHPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VMOVHPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VMOVLPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VMOVLPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSDWYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSDWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSWBYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSWBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSDWYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSDWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSWBYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSWBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPALIGNRYrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPALIGNRrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPBLENDWYrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPBLENDWrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTBYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTWYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDYmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSYmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRWrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXWQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXWQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFBYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFBrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFDYmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFDmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFHWYmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFHWmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFLWYmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFLWmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHBWYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHDQYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHQDQYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHQDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHWDYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLBWYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLBWrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLDQYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLQDQYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLQDQrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLWDYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLWDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPDYrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPDrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPSYrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPSrmi")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPDYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPSYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPSrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPDYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPDrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPSYrm")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPSrm")>;
+
+def SKLWriteResGroup15 : SchedWriteRes<[SKLPort6,SKLPort23]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup15], (instregex "FARJMP64")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "JMP(16|32|64)m")>;
+
+def SKLWriteResGroup16 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup16], (instregex "PABSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PABSDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PABSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PADDSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PADDSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PADDUSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PADDUSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PAVGBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PAVGWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMINSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMINSDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMINSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMINUBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMINUDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PMINUWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNBrm128")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNDrm128")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNWrm128")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSLLDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSLLQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSLLWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSRADrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSRAWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSRLDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSRLQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSRLWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSUBSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSUBSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSUBUSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PSUBUSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPABSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPABSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPABSDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPABSDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPABSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPABSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQQYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNBYrm256")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNBrm128")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNDYrm256")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNDrm128")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNWYrm256")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNWrm128")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLQYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVQYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRADYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRADrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAVDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAVDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLQYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVDYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVDrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVQYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVQrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSWrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSBYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSBrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSWYrm")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSWrm")>;
+
+def SKLWriteResGroup17 : SchedWriteRes<[SKLPort23,SKLPort05]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSBrm64")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSDrm64")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSWrm64")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDBirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDDirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDQirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDWirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PANDNirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PANDirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PORirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNBrm64")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNDrm64")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBBirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBDirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBQirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBWirm")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PXORirm")>;
+
+def SKLWriteResGroup18 : SchedWriteRes<[SKLPort23,SKLPort06]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup18], (instregex "ADC(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "ADC8rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "ADCX32rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "ADCX64rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "ADOX32rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "ADOX64rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "BT(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVAE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVB(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVG(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVGE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVL(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVLE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNO(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNP(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNS(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVO(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVP(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "CMOVS(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "RORX32mi")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "RORX64mi")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SARX32rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SARX64rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SBB(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SBB8rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SHLX32rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SHLX64rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SHRX32rm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "SHRX64rm")>;
+
+def SKLWriteResGroup19 : SchedWriteRes<[SKLPort23,SKLPort15]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup19], (instregex "ANDN32rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "ANDN64rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BLSI32rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BLSI64rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BLSMSK32rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BLSMSK64rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BLSR32rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BLSR64rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BZHI32rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "BZHI64rm")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "MOVBE(16|32|64)rm")>;
+
+def SKLWriteResGroup20 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup20], (instregex "ANDNPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "ANDNPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "ANDPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "ANDPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "BLENDPDrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "BLENDPSrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "ORPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "ORPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PADDBrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PADDDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PADDQrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PADDWrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PANDNrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PANDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PORrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PSUBBrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PSUBDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PSUBQrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PSUBWrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "PXORrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPSYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDPDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDPSYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VANDPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPDYrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPDrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPSYrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPSrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VINSERTF128rm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VINSERTI128rm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPSYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VORPDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VORPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VORPSYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VORPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDBYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDBrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDQYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDQrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDWYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPADDWrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPANDNYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPANDNrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPANDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPANDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPBLENDDYrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPBLENDDrmi")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVQYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVQrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPORYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPORrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBBYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBBrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBQYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBQrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBWYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBWrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPXORYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VPXORrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VXORPDYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VXORPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VXORPSYrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "VXORPSrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "XORPDrm")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "XORPSrm")>;
+
+def SKLWriteResGroup21 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup21], (instregex "ADD(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "ADD8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "AND(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "AND8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mi")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mr")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "CMP8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "OR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "OR8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>;
+
+def SKLWriteResGroup22 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
+  let Latency = 1;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup22], (instregex "SFENCE")>;
+
+def SKLWriteResGroup23 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
+  let Latency = 1;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup23], (instregex "EXTRACTPSmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRBmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRDmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRQmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRWmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "STMXCSR")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "VEXTRACTPSmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRBmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRDmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRQmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRWmr")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "VSTMXCSR")>;
+
+def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
+  let Latency = 1;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup24], (instregex "FNSTCW16m")>;
+
+def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
+  let Latency = 1;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup25], (instregex "SETAEm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETBm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETEm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETGEm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETGm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETLEm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETLm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETNEm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETNOm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETNPm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETNSm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETOm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETPm")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "SETSm")>;
+
+def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
+  let Latency = 1;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup26], (instregex "MOVBE(16|32|64)mr")>;
+
+def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
+  let Latency = 1;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup27], (instregex "PUSH(16|32|64)r(mr?)")>;
+def: InstRW<[SKLWriteResGroup27], (instregex "PUSH64i8")>;
+def: InstRW<[SKLWriteResGroup27], (instregex "STOSB")>;
+def: InstRW<[SKLWriteResGroup27], (instregex "STOSL")>;
+def: InstRW<[SKLWriteResGroup27], (instregex "STOSQ")>;
+def: InstRW<[SKLWriteResGroup27], (instregex "STOSW")>;
+
+def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
+  let Latency = 1;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup28], (instregex "BTC(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "BTR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "BTS(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SAR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SAR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SAR8m1")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SAR8mi")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHL(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHL(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHL8m1")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHL8mi")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHR8m1")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "SHR8mi")>;
+
+def SKLWriteResGroup29 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 1;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup29], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "ADD(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "ADD8mi")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "ADD8mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "AND(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "AND8mi")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "AND8mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "DEC(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "DEC8m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "INC(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "INC8m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "NEG(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "NEG8m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "NOT(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "NOT8m")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "OR(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "OR8mi")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "OR8mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "POP(16|32|64)rmm")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PUSH(16|32|64)rmm")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "SUB(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "SUB8mi")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "SUB8mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "XOR(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "XOR8mi")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "XOR8mr")>;
+
+def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 2;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup31], (instregex "COMISDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "COMISSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_MOVD64from64rr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_MOVD64grr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PMOVMSKBrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MOVMSKPDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MOVMSKPSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MOVPDI2DIrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MOVPQIto64rr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PMOVMSKBrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "UCOMISDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "UCOMISSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VCOMISDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VCOMISSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPDYrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPSYrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VMOVPDI2DIrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VMOVPQIto64rr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPMOVMSKBYrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPMOVMSKBrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPDYrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPSYrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VUCOMISDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VUCOMISSrr")>;
+
+def SKLWriteResGroup32 : SchedWriteRes<[SKLPort5]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup32], (instregex "MMX_MOVQ2DQrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "MMX_PINSRWirri")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "PINSRBrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "PINSRDrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "PINSRQrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "PINSRWrri")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRBrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRDrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRQrr")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRWrri")>;
+
+def SKLWriteResGroup33 : SchedWriteRes<[SKLPort05]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup33], (instregex "FDECSTP")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;
+
+def SKLWriteResGroup34 : SchedWriteRes<[SKLPort06]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup34], (instregex "CMOVA(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "CMOVBE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROL(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROL(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROL8r1")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROL8ri")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROR8r1")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "ROR8ri")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "SETAr")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "SETBEr")>;
+
+def SKLWriteResGroup35 : SchedWriteRes<[SKLPort015]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup35], (instregex "BLENDVPDrr0")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "BLENDVPSrr0")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "PBLENDVBrr0")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPDYrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPDrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPSYrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPSrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "VPBLENDVBYrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "VPBLENDVBrr")>;
+
+def SKLWriteResGroup36 : SchedWriteRes<[SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup36], (instregex "LFENCE")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "WAIT")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "XGETBV")>;
+
+def SKLWriteResGroup37 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup37], (instregex "COMISDrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "COMISSrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "UCOMISDrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "UCOMISSrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VCOMISDrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VCOMISSrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPDYrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPDrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPSYrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPSrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VUCOMISDrm")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "VUCOMISSrm")>;
+
+def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup38], (instregex "PSLLDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSLLQrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSLLWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSRADrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSRAWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSRLDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSRLQrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PSRLWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLQrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSRADrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSRAWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLQrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLWrr")>;
+
+def SKLWriteResGroup39 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup39], (instregex "CLFLUSH")>;
+
+def SKLWriteResGroup40 : SchedWriteRes<[SKLPort06,SKLPort15]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup40], (instregex "BEXTR32rr")>;
+def: InstRW<[SKLWriteResGroup40], (instregex "BEXTR64rr")>;
+def: InstRW<[SKLWriteResGroup40], (instregex "BSWAP(16|32|64)r")>;
+
+def SKLWriteResGroup41 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup41], (instregex "ADC8i8")>;
+def: InstRW<[SKLWriteResGroup41], (instregex "ADC8ri")>;
+def: InstRW<[SKLWriteResGroup41], (instregex "CWD")>;
+def: InstRW<[SKLWriteResGroup41], (instregex "JRCXZ")>;
+def: InstRW<[SKLWriteResGroup41], (instregex "SBB8i8")>;
+def: InstRW<[SKLWriteResGroup41], (instregex "SBB8ri")>;
+
+def SKLWriteResGroup42 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKSSDWirm")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKSSWBirm")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKUSWBirm")>;
+
+def SKLWriteResGroup43 : SchedWriteRes<[SKLPort23,SKLPort06]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup43], (instregex "CMOVA(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup43], (instregex "CMOVBE(16|32|64)rm")>;
+
+def SKLWriteResGroup44 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup44], (instregex "BLENDVPDrm0")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "BLENDVPSrm0")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "PBLENDVBrm0")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPDYrm")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPDrm")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPSYrm")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPSrm")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "VPBLENDVBYrm")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "VPBLENDVBrm")>;
+
+def SKLWriteResGroup45 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup45], (instregex "LEAVE64")>;
+def: InstRW<[SKLWriteResGroup45], (instregex "SCASB")>;
+def: InstRW<[SKLWriteResGroup45], (instregex "SCASL")>;
+def: InstRW<[SKLWriteResGroup45], (instregex "SCASQ")>;
+def: InstRW<[SKLWriteResGroup45], (instregex "SCASW")>;
+
+def SKLWriteResGroup46 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup46], (instregex "MFENCE")>;
+
+def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup47], (instregex "FNSTSWm")>;
+
+def SKLWriteResGroup48 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup48], (instregex "FLDCW16m")>;
+
+def SKLWriteResGroup49 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup49], (instregex "LDMXCSR")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VLDMXCSR")>;
+
+def SKLWriteResGroup51 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup51], (instregex "LRETQ")>;
+def: InstRW<[SKLWriteResGroup51], (instregex "RETQ")>;
+
+def SKLWriteResGroup52 : SchedWriteRes<[SKLPort23,SKLPort06,SKLPort15]> {
+  let Latency = 2;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup52], (instregex "BEXTR32rm")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "BEXTR64rm")>;
+
+def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
+  let Latency = 2;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,2];
+}
+def: InstRW<[SKLWriteResGroup53], (instregex "SETAm")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "SETBEm")>;
+
+def SKLWriteResGroup54 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup54], (instregex "CALL(16|32|64)r")>;
+
+def SKLWriteResGroup55 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup55], (instregex "CALL64pcrel32")>;
+
+def SKLWriteResGroup56 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
+  let Latency = 2;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup56], (instregex "ROL(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROL(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROL8m1")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROL8mi")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROR8m1")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "ROR8mi")>;
+
+def SKLWriteResGroup57 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup57], (instregex "XADD(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup57], (instregex "XADD8rm")>;
+
+def SKLWriteResGroup58 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 2;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup58], (instregex "CALL(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "FARCALL64")>;
+
+def SKLWriteResGroup60 : SchedWriteRes<[SKLPort1]> {
+  let Latency = 3;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup60], (instregex "BSF(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "BSR(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "IMUL64rr(i8?)")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "IMUL8r")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "LZCNT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "MUL8r")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "PDEP32rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "PDEP64rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "PEXT32rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "PEXT64rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "POPCNT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "SHLD(16|32|64)rri8")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "SHRD(16|32|64)rri8")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "TZCNT(16|32|64)rr")>;
+
+def SKLWriteResGroup60_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup60_16], (instregex "IMUL16rr(i8?)")>;
+
+def SKLWriteResGroup60_32 : SchedWriteRes<[SKLPort1]> {
+  let Latency = 3;
+  let NumMicroOps = 1;
+}
+def: InstRW<[SKLWriteResGroup60_32], (instregex "IMUL32rr(i8?)")>;
+
+def SKLWriteResGroup61 : SchedWriteRes<[SKLPort5]> {
+  let Latency = 3;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FPrST0")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FST0r")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FrST0")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "MMX_PSADBWirr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "PCMPGTQrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "PSADBWrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FPrST0")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FST0r")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FrST0")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FPrST0")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FST0r")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FrST0")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VBROADCASTSDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VBROADCASTSSYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VEXTRACTF128rr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VEXTRACTI128rr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VINSERTF128rr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VINSERTI128rr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTBYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTBrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTWYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTWrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPCMPGTQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPCMPGTQrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPERM2F128rr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPERM2I128rr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPERMDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPERMPDYri")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPERMPSYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPERMQYri")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBWYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXDQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXWDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXWQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBWYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXDQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXWDYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXWQYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPSADBWYrr")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "VPSADBWrr")>;
+
+def SKLWriteResGroup62 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup62], (instregex "EXTRACTPSrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "MMX_PEXTRWirri")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRBrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRDrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRQrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRWri")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRWrr_REV")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "PTESTrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VEXTRACTPSrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRBrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRDrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRQrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRWri")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRWrr_REV")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPTESTYrr")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "VPTESTrr")>;
+
+def SKLWriteResGroup63 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup63], (instregex "FNSTSW16r")>;
+
+def SKLWriteResGroup64 : SchedWriteRes<[SKLPort1,SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup64], (instregex "BSF(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "BSR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "IMUL64m")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "IMUL(32|64)rm(i8?)")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "IMUL8m")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "LZCNT(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "MUL64m")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "MUL8m")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "PDEP32rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "PDEP64rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "PEXT32rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "PEXT64rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "POPCNT(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "TZCNT(16|32|64)rm")>;
+
+def SKLWriteResGroup64_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1]; 
+}
+def: InstRW<[SKLWriteResGroup64_16], (instregex "IMUL16rm(i8?)")>;
+
+def SKLWriteResGroup64_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 5;
+}
+def: InstRW<[SKLWriteResGroup64_16_2], (instregex "IMUL16m")>;
+def: InstRW<[SKLWriteResGroup64_16_2], (instregex "MUL16m")>;
+
+def SKLWriteResGroup64_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup64_32], (instregex "IMUL32m")>;
+def: InstRW<[SKLWriteResGroup64_32], (instregex "MUL32m")>;
+
+def SKLWriteResGroup65 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup65], (instregex "ADD_F32m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "ADD_F64m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F16m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F32m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F64m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "MMX_PSADBWirm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "PCMPGTQrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "PSADBWrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "SUBR_F32m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "SUBR_F64m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "SUB_F32m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "SUB_F64m")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPCMPGTQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPCMPGTQrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPERM2F128rm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPERM2I128rm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPERMDYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPERMPDYmi")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPERMPSYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPERMQYmi")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBDYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBWYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXDQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXWDYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXWQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBDYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBWYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXDQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXWDYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXWQYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPSADBWYrm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "VPSADBWrm")>;
+
+def SKLWriteResGroup66 : SchedWriteRes<[SKLPort06]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [3];
+}
+def: InstRW<[SKLWriteResGroup66], (instregex "ROL(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "ROL8rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "ROR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "ROR8rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "SAR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "SAR8rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "SHL(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "SHL8rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "SHR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "SHR8rCL")>;
+
+def SKLWriteResGroup67 : SchedWriteRes<[SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [3];
+}
+def: InstRW<[SKLWriteResGroup67], (instregex "XADD(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "XADD8rr")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "XCHG8rr")>;
+
+def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup68], (instregex "MMX_PHADDSWrr64")>;
+def: InstRW<[SKLWriteResGroup68], (instregex "MMX_PHSUBSWrr64")>;
+
+def SKLWriteResGroup69 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup69], (instregex "PHADDSWrr128")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "PHSUBSWrr128")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "VPHADDSWrr128")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "VPHADDSWrr256")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "VPHSUBSWrr128")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "VPHSUBSWrr256")>;
+
+def SKLWriteResGroup70 : SchedWriteRes<[SKLPort5,SKLPort05]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHADDWrr64")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHADDrr64")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHSUBDrr64")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHSUBWrr64")>;
+
+def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup71], (instregex "PHADDDrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PHADDWrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PHSUBDrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PHSUBWrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDDYrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDDrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDWYrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDWrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBDYrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBDrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBWYrr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBWrr")>;
+
+def SKLWriteResGroup72 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKSSDWirr")>;
+def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKSSWBirr")>;
+def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKUSWBirr")>;
+
+def SKLWriteResGroup73 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup73], (instregex "CLD")>;
+
+def SKLWriteResGroup74 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup74], (instregex "RCL(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCL(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCL8r1")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCL8ri")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCR8r1")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RCR8ri")>;
+
+def SKLWriteResGroup75 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup75], (instregex "PTESTrm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "VPTESTYrm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "VPTESTrm")>;
+
+def SKLWriteResGroup76 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP16m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP32m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP64m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "IST_F16m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "IST_F32m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP16m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP32m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP64m")>;
+
+def SKLWriteResGroup77 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,2,1];
+}
+def: InstRW<[SKLWriteResGroup77], (instregex "MMX_PHADDSWrm64")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "MMX_PHSUBSWrm64")>;
+
+def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 4;
+  let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup78], (instregex "PHADDSWrm128")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "PHSUBSWrm128")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "VPHADDSWrm128")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "VPHADDSWrm256")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "VPHSUBSWrm128")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "VPHSUBSWrm256")>;
+
+def SKLWriteResGroup79 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
+  let Latency = 3;
+  let NumMicroOps = 4;
+  let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHADDWrm64")>;
+def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHADDrm64")>;
+def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHSUBDrm64")>;
+def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHSUBWrm64")>;
+
+def SKLWriteResGroup80 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+  let Latency = 3;
+  let NumMicroOps = 4;
+  let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup80], (instregex "PHADDDrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "PHADDWrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "PHSUBDrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "PHSUBWrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDDYrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDDrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDWYrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDWrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBDYrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBDrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBWYrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBWrm")>;
+
+def SKLWriteResGroup81 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
+  let Latency = 3;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,1,3];
+}
+def: InstRW<[SKLWriteResGroup81], (instregex "ROR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup81], (instregex "ROR8mCL")>;
+
+def SKLWriteResGroup82 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup82], (instregex "RCL(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCL(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCL8m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCL8mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCR8m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "RCR8mi")>;
+
+def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
+  let Latency = 3;
+  let NumMicroOps = 6;
+  let ResourceCycles = [1,1,1,3];
+}
+def: InstRW<[SKLWriteResGroup83], (instregex "ROL(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "ROL8mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SAR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SAR8mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SHL(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SHL8mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SHR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SHR8mCL")>;
+
+def SKLWriteResGroup84 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 6;
+  let ResourceCycles = [1,1,1,3];
+}
+def: InstRW<[SKLWriteResGroup84], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup84], (instregex "ADC8mi")>;
+
+def SKLWriteResGroup85 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 3;
+  let NumMicroOps = 6;
+  let ResourceCycles = [1,1,1,2,1];
+}
+def: InstRW<[SKLWriteResGroup85], (instregex "ADC(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "ADC8mr")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "CMPXCHG(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "CMPXCHG8rm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "SBB(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "SBB8mi")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "SBB8mr")>;
+
+def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 4;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup86], (instregex "AESDECLASTrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "AESDECrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "AESENCLASTrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "AESENCrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMADDUBSWrr64")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMADDWDirr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHUWirr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHWirr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULLWirr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULUDQirr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FPrST0")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FST0r")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FrST0")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "RCPPSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "RCPSSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "RSQRTPSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "RSQRTSSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VAESDECLASTrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VAESDECrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VAESENCLASTrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VAESENCrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VRCPPSYr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VRCPPSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VRCPSSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTPSYr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTPSr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTSSr")>;
+
+def SKLWriteResGroup87 : SchedWriteRes<[SKLPort01]> {
+  let Latency = 4;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup87], (instregex "ADDPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "ADDPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "ADDSDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "ADDSSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "ADDSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "ADDSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "MULPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "MULPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "MULSDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "MULSSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "SUBPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "SUBPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "SUBSDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "SUBSSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDPDYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDPSYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDSDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDSSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPDYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPSYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PDYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PSYr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231SDr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231SSr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VMULPDYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VMULPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VMULPSYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VMULPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VMULSDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VMULSSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPDYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPSYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VSUBSDrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VSUBSSrr")>;
+
+def SKLWriteResGroup89 : SchedWriteRes<[SKLPort015]> {
+  let Latency = 4;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup89], (instregex "CMPPDrri")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "CMPPSrri")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "CMPSSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "CVTDQ2PSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "CVTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "CVTTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MAXPDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MAXPSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MAXSDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MAXSSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MINPDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MINPSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MINSDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "MINSSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMADDUBSWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMADDWDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMULDQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMULHRSWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMULHUWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMULHWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMULLWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "PMULUDQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPDYrri")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPDrri")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPSYrri")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPSrri")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCMPSDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCMPSSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTDQ2PSYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTDQ2PSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2DQYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPS2DQYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPDYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPSYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMAXSDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMAXSSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMINPDYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMINPDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMINPSYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMINPSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMINSDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VMINSSrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDUBSWYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDUBSWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDWDYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDWDrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULDQYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULDQrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHRSWYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHRSWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHUWYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHUWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHWYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULLWYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULLWrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULUDQYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VPMULUDQrr")>;
+
+def SKLWriteResGroup90 : SchedWriteRes<[SKLPort5]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup90], (instregex "MPSADBWrri")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VMPSADBWYrri")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VMPSADBWrri")>;
+
+def SKLWriteResGroup91 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup91], (instregex "AESDECLASTrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "AESDECrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "AESENCLASTrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "AESENCrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_CVTPI2PSirm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMADDUBSWrm64")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMADDWDirm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHUWirm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHWirm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULLWirm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULUDQirm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MUL_F32m")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "MUL_F64m")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "RCPPSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "RCPSSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "RSQRTPSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "RSQRTSSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VAESDECLASTrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VAESDECrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VAESENCLASTrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VAESENCrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VRCPPSYm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VRCPPSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VRCPSSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTPSYm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTPSm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTSSm")>;
+
+def SKLWriteResGroup92 : SchedWriteRes<[SKLPort1,SKLPort5]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup92], (instregex "IMUL64r")>;
+def: InstRW<[SKLWriteResGroup92], (instregex "MUL64r")>;
+def: InstRW<[SKLWriteResGroup92], (instregex "MULX64rr")>;
+
+def SKLWriteResGroup92_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 4;  
+}
+def: InstRW<[SKLWriteResGroup92_16], (instregex "IMUL16r")>;
+def: InstRW<[SKLWriteResGroup92_16], (instregex "MUL16r")>;
+
+def SKLWriteResGroup93 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLDYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLQYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLWYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSRADYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSRAWYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLDYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLQYrr")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLWYrr")>;
+
+def SKLWriteResGroup94 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup94], (instregex "ADDPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "ADDPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "ADDSDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "ADDSSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "ADDSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "ADDSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "MULPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "MULPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "MULSDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "MULSSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SUBPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SUBPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SUBSDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SUBSSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDPDYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDPSYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDSDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDSSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPDYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPSYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PDYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PSYm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231SDm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231SSm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VMULPDYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VMULPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VMULPSYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VMULPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VMULSDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VMULSSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPDYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPSYrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VSUBSDrm")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "VSUBSSrm")>;
+
+def SKLWriteResGroup96 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup96], (instregex "CMPPDrmi")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CMPPSrmi")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CMPSSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CVTDQ2PSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CVTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CVTPS2PDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CVTSS2SDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "CVTTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MAXPDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MAXPSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MAXSDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MAXSSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MINPDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MINPSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MINSDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MINSSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MMX_CVTPS2PIirm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "MMX_CVTTPS2PIirm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMADDUBSWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMADDWDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMULDQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMULHRSWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMULHUWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMULHWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMULLWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "PMULUDQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPDYrmi")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPDrmi")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPSYrmi")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPSrmi")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCMPSDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCMPSSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTDQ2PSYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTDQ2PSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPH2PSYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPH2PSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2DQYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2PDYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2PDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTSS2SDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTTPS2DQYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VCVTTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPDYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPSYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMAXSDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMAXSSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMINPDYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMINPDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMINPSYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMINPSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMINSDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VMINSSrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDUBSWYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDUBSWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDWDYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDWDrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULDQYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULDQrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHRSWYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHRSWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHUWYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHUWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHWYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULLWYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULLWrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULUDQYrm")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "VPMULUDQrm")>;
+
+def SKLWriteResGroup97 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+  let Latency = 4;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup97], (instregex "FICOM16m")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "FICOM32m")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "FICOMP16m")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "FICOMP32m")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "MPSADBWrmi")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "VMPSADBWYrmi")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "VMPSADBWrmi")>;
+
+def SKLWriteResGroup98 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
+  let Latency = 4;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup98], (instregex "MULX64rm")>;
+
+def SKLWriteResGroup100 : SchedWriteRes<[SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 4;
+  let ResourceCycles = [4];
+}
+def: InstRW<[SKLWriteResGroup100], (instregex "FNCLEX")>;
+
+def SKLWriteResGroup101 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,3];
+}
+def: InstRW<[SKLWriteResGroup101], (instregex "PAUSE")>;
+
+def SKLWriteResGroup102 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,3];
+}
+def: InstRW<[SKLWriteResGroup102], (instregex "VZEROUPPER")>;
+
+def SKLWriteResGroup103 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,2];
+}
+def: InstRW<[SKLWriteResGroup103], (instregex "LAR(16|32|64)rr")>;
+
+def SKLWriteResGroup105 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup105], (instregex "SHLD(16|32|64)mri8")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "SHRD(16|32|64)mri8")>;
+
+def SKLWriteResGroup106 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,2,1,1];
+}
+def: InstRW<[SKLWriteResGroup106], (instregex "LAR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup106], (instregex "LSL(16|32|64)rm")>;
+
+def SKLWriteResGroup107 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
+  let Latency = 4;
+  let NumMicroOps = 6;
+  let ResourceCycles = [1,1,4];
+}
+def: InstRW<[SKLWriteResGroup107], (instregex "PUSHF16")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PUSHF64")>;
+
+def SKLWriteResGroup109 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+  let Latency = 5;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup109], (instregex "CVTDQ2PDrr")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "MMX_CVTPI2PDirr")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VCVTDQ2PDrr")>;
+
+def SKLWriteResGroup110 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+  let Latency = 5;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTPD2PSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTPS2PDrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTSD2SSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SD64rr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SDrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTSS2SDrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "CVTTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTPD2PIirr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTPS2PIirr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTTPD2PIirr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTTPS2PIirr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPD2PSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPH2PSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPS2PDrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPS2PHrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSD2SSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SD64rr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SDrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SSrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSS2SDrr")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VCVTTPD2DQrr")>;
+
+def SKLWriteResGroup113 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+  let Latency = 5;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup113], (instregex "CVTDQ2PDrm")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_CVTPI2PDirm")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "VCVTDQ2PDrm")>;
+
+def SKLWriteResGroup114 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
+  let Latency = 5;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup114], (instregex "STR(16|32|64)r")>;
+
+def SKLWriteResGroup115 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+  let Latency = 5;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup115], (instregex "IMUL32r")>;
+def: InstRW<[SKLWriteResGroup115], (instregex "MUL32r")>;
+def: InstRW<[SKLWriteResGroup115], (instregex "MULX32rr")>;
+
+def SKLWriteResGroup116 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+  let Latency = 5;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup116], (instregex "CVTPD2DQrm")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "CVTPD2PSrm")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "CVTSD2SSrm")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "CVTTPD2DQrm")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "MMX_CVTPD2PIirm")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "MMX_CVTTPD2PIirm")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "VCVTSD2SSrm")>;
+
+def SKLWriteResGroup118 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
+  let Latency = 5;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup118], (instregex "MULX32rm")>;
+
+def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
+  let Latency = 5;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup119], (instregex "VCVTPS2PHmr")>;
+
+def SKLWriteResGroup120 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+  let Latency = 5;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,4];
+}
+def: InstRW<[SKLWriteResGroup120], (instregex "XSETBV")>;
+
+def SKLWriteResGroup121 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+  let Latency = 5;
+  let NumMicroOps = 5;
+  let ResourceCycles = [2,3];
+}
+def: InstRW<[SKLWriteResGroup121], (instregex "CMPXCHG(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "CMPXCHG8rr")>;
+
+def SKLWriteResGroup122 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 5;
+  let NumMicroOps = 8;
+  let ResourceCycles = [1,1,1,1,1,3];
+}
+def: InstRW<[SKLWriteResGroup122], (instregex "ADD8mi")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "AND8mi")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "OR8mi")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "SUB8mi")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "XCHG(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "XCHG8rm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "XOR8mi")>;
+
+def SKLWriteResGroup123 : SchedWriteRes<[SKLPort5]> {
+  let Latency = 6;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup123], (instregex "PCLMULQDQrr")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VPCLMULQDQrr")>;
+
+def SKLWriteResGroup124 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 6;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup124], (instregex "MMX_CVTPI2PSirr")>;
+
+def SKLWriteResGroup125 : SchedWriteRes<[SKLPort0,SKLPort015]> {
+  let Latency = 6;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup125], (instregex "CVTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "CVTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "CVTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "CVTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "CVTTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "CVTTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VCVTTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VCVTTSD2SIrr")>;
+
+def SKLWriteResGroup126 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+  let Latency = 6;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup126], (instregex "PCLMULQDQrm")>;
+def: InstRW<[SKLWriteResGroup126], (instregex "VPCLMULQDQrm")>;
+
+def SKLWriteResGroup127 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+  let Latency = 6;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup127], (instregex "HADDPDrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "HADDPSrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "HSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "HSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPDYrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPDrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPSYrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPSrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPDYrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPSYrr")>;
+def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPSrr")>;
+
+def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+  let Latency = 6;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup128], (instregex "ADD_FI16m")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "ADD_FI32m")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "SUBR_FI16m")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "SUBR_FI32m")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "SUB_FI16m")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "SUB_FI32m")>;
+
+def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+  let Latency = 6;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup129], (instregex "CVTSI2SS64rr")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "VCVTSI2SS64rr")>;
+
+def SKLWriteResGroup130 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {
+  let Latency = 6;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSS2SIrm")>;
+
+def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+  let Latency = 6;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,2,1];
+}
+def: InstRW<[SKLWriteResGroup131], (instregex "SHLD(16|32|64)rrCL")>;
+def: InstRW<[SKLWriteResGroup131], (instregex "SHRD(16|32|64)rrCL")>;
+
+def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+  let Latency = 6;
+  let NumMicroOps = 4;
+  let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup133], (instregex "HADDPDrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "HADDPSrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "HSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "HSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPDYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPDrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPSYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPSrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPDYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPSYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPSrm")>;
+
+def SKLWriteResGroup134 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
+  let Latency = 6;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup134], (instregex "SLDT(16|32|64)r")>;
+
+def SKLWriteResGroup136 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+  let Latency = 6;
+  let NumMicroOps = 6;
+  let ResourceCycles = [1,5];
+}
+def: InstRW<[SKLWriteResGroup136], (instregex "STD")>;
+
+def SKLWriteResGroup137 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 6;
+  let NumMicroOps = 6;
+  let ResourceCycles = [1,1,1,2,1];
+}
+def: InstRW<[SKLWriteResGroup137], (instregex "SHLD(16|32|64)mrCL")>;
+def: InstRW<[SKLWriteResGroup137], (instregex "SHRD(16|32|64)mrCL")>;
+
+def SKLWriteResGroup142 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+  let Latency = 7;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup142], (instregex "VCVTDQ2PDYrr")>;
+
+def SKLWriteResGroup143 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+  let Latency = 7;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPD2DQYrr")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPD2PSYrr")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPH2PSYrr")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPS2PDYrr")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPS2PHYrr")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "VCVTTPD2DQYrr")>;
+
+def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+  let Latency = 7;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup145], (instregex "MUL_FI16m")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "MUL_FI32m")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "VCVTDQ2PDYrm")>;
+
+def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
+  let Latency = 7;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup146], (instregex "CVTTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup146], (instregex "CVTTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup146], (instregex "VCVTTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup146], (instregex "VCVTTSS2SIrr")>;
+
+def SKLWriteResGroup149 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
+  let Latency = 7;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup149], (instregex "CVTTSS2SI64rm")>;
+
+def SKLWriteResGroup150 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
+  let Latency = 7;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup150], (instregex "VCVTPS2PHYmr")>;
+
+def SKLWriteResGroup151 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 7;
+  let NumMicroOps = 7;
+  let ResourceCycles = [1,3,1,2];
+}
+def: InstRW<[SKLWriteResGroup151], (instregex "LOOP")>;
+
+def SKLWriteResGroup156 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 8;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup156], (instregex "AESIMCrr")>;
+def: InstRW<[SKLWriteResGroup156], (instregex "VAESIMCrr")>;
+
+def SKLWriteResGroup157 : SchedWriteRes<[SKLPort015]> {
+  let Latency = 8;
+  let NumMicroOps = 2;
+  let ResourceCycles = [2];
+}
+def: InstRW<[SKLWriteResGroup157], (instregex "PMULLDrr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDPDr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDPSr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDSDr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDSSr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VPMULLDYrr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VPMULLDrr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDPDr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDPSr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDSDr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDSSr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDYPDr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDYPSr")>;
+
+def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 8;
+  let NumMicroOps = 3;
+  let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup160], (instregex "AESIMCrm")>;
+def: InstRW<[SKLWriteResGroup160], (instregex "VAESIMCrm")>;
+
+def SKLWriteResGroup161 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+  let Latency = 8;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup161], (instregex "PMULLDrm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDPDm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDPSm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDSDm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDSSm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VPMULLDYrm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VPMULLDrm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDPDm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDPSm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDSDm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDSSm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDYPDm")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDYPSm")>;
+
+def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+  let Latency = 9;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup165], (instregex "DPPDrri")>;
+def: InstRW<[SKLWriteResGroup165], (instregex "VDPPDrri")>;
+
+def SKLWriteResGroup167 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+  let Latency = 9;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,1,2];
+}
+def: InstRW<[SKLWriteResGroup167], (instregex "DPPDrmi")>;
+def: InstRW<[SKLWriteResGroup167], (instregex "VDPPDrmi")>;
+
+def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 10;
+  let NumMicroOps = 3;
+  let ResourceCycles = [3];
+}
+def: InstRW<[SKLWriteResGroup169], (instregex "PCMPISTRIrr")>;
+def: InstRW<[SKLWriteResGroup169], (instregex "PCMPISTRM128rr")>;
+def: InstRW<[SKLWriteResGroup169], (instregex "VPCMPISTRIrr")>;
+def: InstRW<[SKLWriteResGroup169], (instregex "VPCMPISTRM128rr")>;
+
+def SKLWriteResGroup170 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 10;
+  let NumMicroOps = 4;
+  let ResourceCycles = [3,1];
+}
+def: InstRW<[SKLWriteResGroup170], (instregex "PCMPISTRIrm")>;
+def: InstRW<[SKLWriteResGroup170], (instregex "PCMPISTRM128rm")>;
+def: InstRW<[SKLWriteResGroup170], (instregex "VPCMPISTRIrm")>;
+def: InstRW<[SKLWriteResGroup170], (instregex "VPCMPISTRM128rm")>;
+
+def SKLWriteResGroup171 : SchedWriteRes<[SKLPort05,SKLPort0156]> {
+  let Latency = 10;
+  let NumMicroOps = 10;
+  let ResourceCycles = [9,1];
+}
+def: InstRW<[SKLWriteResGroup171], (instregex "MMX_EMMS")>;
+
+def SKLWriteResGroup172 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 10;
+  let NumMicroOps = 10;
+  let ResourceCycles = [1,1,1,5,1,1];
+}
+def: InstRW<[SKLWriteResGroup172], (instregex "RCL(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup172], (instregex "RCL8mCL")>;
+
+def SKLWriteResGroup173 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 11;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup173], (instregex "DIVPSrr")>;
+def: InstRW<[SKLWriteResGroup173], (instregex "DIVSSrr")>;
+def: InstRW<[SKLWriteResGroup173], (instregex "VDIVPSYrr")>;
+def: InstRW<[SKLWriteResGroup173], (instregex "VDIVPSrr")>;
+def: InstRW<[SKLWriteResGroup173], (instregex "VDIVSSrr")>;
+
+def SKLWriteResGroup174 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 11;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup174], (instregex "DIVPSrm")>;
+def: InstRW<[SKLWriteResGroup174], (instregex "DIVSSrm")>;
+def: InstRW<[SKLWriteResGroup174], (instregex "VDIVPSYrm")>;
+def: InstRW<[SKLWriteResGroup174], (instregex "VDIVPSrm")>;
+def: InstRW<[SKLWriteResGroup174], (instregex "VDIVSSrm")>;
+
+def SKLWriteResGroup175 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+  let Latency = 11;
+  let NumMicroOps = 7;
+  let ResourceCycles = [2,3,2];
+}
+def: InstRW<[SKLWriteResGroup175], (instregex "RCL(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup175], (instregex "RCR(16|32|64)rCL")>;
+
+def SKLWriteResGroup176 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 11;
+  let NumMicroOps = 9;
+  let ResourceCycles = [1,5,1,2];
+}
+def: InstRW<[SKLWriteResGroup176], (instregex "RCL8rCL")>;
+
+def SKLWriteResGroup177 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+  let Latency = 11;
+  let NumMicroOps = 11;
+  let ResourceCycles = [2,9];
+}
+def: InstRW<[SKLWriteResGroup177], (instregex "LOOPE")>;
+def: InstRW<[SKLWriteResGroup177], (instregex "LOOPNE")>;
+
+def SKLWriteResGroup178 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 11;
+  let NumMicroOps = 14;
+  let ResourceCycles = [1,1,1,4,2,5];
+}
+def: InstRW<[SKLWriteResGroup178], (instregex "CMPXCHG8B")>;
+
+def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 12;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTPSYr")>;
+def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTPSr")>;
+def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTSSr")>;
+
+def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 12;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTPSYm")>;
+def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTPSm")>;
+def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTSSm")>;
+
+def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 13;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup181], (instregex "SQRTPSr")>;
+def: InstRW<[SKLWriteResGroup181], (instregex "SQRTSSr")>;
+
+def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 13;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup182], (instregex "SQRTPSm")>;
+def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm")>;
+
+def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+  let Latency = 13;
+  let NumMicroOps = 4;
+  let ResourceCycles = [1,3];
+}
+def: InstRW<[SKLWriteResGroup187], (instregex "DPPSrri")>;
+def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSYrri")>;
+def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSrri")>;
+
+def SKLWriteResGroup188 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+  let Latency = 13;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,1,3];
+}
+def: InstRW<[SKLWriteResGroup188], (instregex "DPPSrmi")>;
+def: InstRW<[SKLWriteResGroup188], (instregex "VDPPSYrmi")>;
+def: InstRW<[SKLWriteResGroup188], (instregex "VDPPSrmi")>;
+
+def SKLWriteResGroup189 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 13;
+  let NumMicroOps = 11;
+  let ResourceCycles = [2,1,1,4,1,2];
+}
+def: InstRW<[SKLWriteResGroup189], (instregex "RCR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup189], (instregex "RCR8mCL")>;
+
+def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 14;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup190], (instregex "DIVPDrr")>;
+def: InstRW<[SKLWriteResGroup190], (instregex "DIVSDrr")>;
+def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDYrr")>;
+def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDrr")>;
+def: InstRW<[SKLWriteResGroup190], (instregex "VDIVSDrr")>;
+
+def SKLWriteResGroup191 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 14;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup191], (instregex "DIVPDrm")>;
+def: InstRW<[SKLWriteResGroup191], (instregex "DIVSDrm")>;
+def: InstRW<[SKLWriteResGroup191], (instregex "VDIVPDYrm")>;
+def: InstRW<[SKLWriteResGroup191], (instregex "VDIVPDrm")>;
+def: InstRW<[SKLWriteResGroup191], (instregex "VDIVSDrm")>;
+
+def SKLWriteResGroup192 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 14;
+  let NumMicroOps = 10;
+  let ResourceCycles = [2,4,1,3];
+}
+def: InstRW<[SKLWriteResGroup192], (instregex "RCR8rCL")>;
+
+def SKLWriteResGroup193 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 15;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FPrST0")>;
+def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FST0r")>;
+def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FrST0")>;
+
+def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 15;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup194], (instregex "DIV_F32m")>;
+def: InstRW<[SKLWriteResGroup194], (instregex "DIV_F64m")>;
+
+def SKLWriteResGroup195 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 15;
+  let NumMicroOps = 8;
+  let ResourceCycles = [1,1,1,1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup195], (instregex "INSB")>;
+def: InstRW<[SKLWriteResGroup195], (instregex "INSL")>;
+def: InstRW<[SKLWriteResGroup195], (instregex "INSW")>;
+
+def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0156]> {
+  let Latency = 16;
+  let NumMicroOps = 16;
+  let ResourceCycles = [16];
+}
+def: InstRW<[SKLWriteResGroup196], (instregex "VZEROALL")>;
+
+def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
+  let Latency = 17;
+  let NumMicroOps = 15;
+  let ResourceCycles = [2,1,2,4,2,4];
+}
+def: InstRW<[SKLWriteResGroup197], (instregex "XCH_F")>;
+
+def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 18;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTPDYr")>;
+def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTPDr")>;
+def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTSDr")>;
+
+def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 18;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDYm")>;
+def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;
+def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTSDm")>;
+
+def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+  let Latency = 18;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup200], (instregex "DIV_FI16m")>;
+def: InstRW<[SKLWriteResGroup200], (instregex "DIV_FI32m")>;
+
+def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {
+  let Latency = 18;
+  let NumMicroOps = 8;
+  let ResourceCycles = [4,3,1];
+}
+def: InstRW<[SKLWriteResGroup201], (instregex "PCMPESTRIrr")>;
+def: InstRW<[SKLWriteResGroup201], (instregex "VPCMPESTRIrr")>;
+
+def SKLWriteResGroup202 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
+  let Latency = 18;
+  let NumMicroOps = 8;
+  let ResourceCycles = [1,1,1,5];
+}
+def: InstRW<[SKLWriteResGroup202], (instregex "CPUID")>;
+def: InstRW<[SKLWriteResGroup202], (instregex "RDTSC")>;
+
+def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
+  let Latency = 18;
+  let NumMicroOps = 9;
+  let ResourceCycles = [4,3,1,1];
+}
+def: InstRW<[SKLWriteResGroup203], (instregex "PCMPESTRIrm")>;
+def: InstRW<[SKLWriteResGroup203], (instregex "VPCMPESTRIrm")>;
+
+def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 18;
+  let NumMicroOps = 19;
+  let ResourceCycles = [2,1,4,1,1,4,6];
+}
+def: InstRW<[SKLWriteResGroup204], (instregex "CMPXCHG16B")>;
+
+def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {
+  let Latency = 19;
+  let NumMicroOps = 9;
+  let ResourceCycles = [4,3,1,1];
+}
+def: InstRW<[SKLWriteResGroup205], (instregex "PCMPESTRM128rr")>;
+def: InstRW<[SKLWriteResGroup205], (instregex "VPCMPESTRM128rr")>;
+
+def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {
+  let Latency = 19;
+  let NumMicroOps = 10;
+  let ResourceCycles = [4,3,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup206], (instregex "PCMPESTRM128rm")>;
+def: InstRW<[SKLWriteResGroup206], (instregex "VPCMPESTRM128rm")>;
+
+def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
+  let Latency = 19;
+  let NumMicroOps = 11;
+  let ResourceCycles = [3,6,1,1];
+}
+def: InstRW<[SKLWriteResGroup207], (instregex "AESKEYGENASSIST128rm")>;
+def: InstRW<[SKLWriteResGroup207], (instregex "VAESKEYGENASSIST128rm")>;
+
+def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0]> {
+  let Latency = 20;
+  let NumMicroOps = 1;
+  let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FPrST0")>;
+def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FST0r")>;
+def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FrST0")>;
+def: InstRW<[SKLWriteResGroup208], (instregex "SQRTPDr")>;
+def: InstRW<[SKLWriteResGroup208], (instregex "SQRTSDr")>;
+
+def SKLWriteResGroup209 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+  let Latency = 20;
+  let NumMicroOps = 2;
+  let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup209], (instregex "DIVR_F32m")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "DIVR_F64m")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "SQRTPDm")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "SQRTSDm")>;
+
+def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
+  let Latency = 20;
+  let NumMicroOps = 10;
+  let ResourceCycles = [1,2,7];
+}
+def: InstRW<[SKLWriteResGroup210], (instregex "MWAITrr")>;
+
+def SKLWriteResGroup211 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
+  let Latency = 20;
+  let NumMicroOps = 11;
+  let ResourceCycles = [3,6,2];
+}
+def: InstRW<[SKLWriteResGroup211], (instregex "AESKEYGENASSIST128rr")>;
+def: InstRW<[SKLWriteResGroup211], (instregex "VAESKEYGENASSIST128rr")>;
+
+def SKLWriteResGroup212 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
+  let Latency = 17;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,2,1,1];
+}
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPSrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPSrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDQrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQQrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDQrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQQrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPSrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPSrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPDrm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPDrm")>;
+
+def SKLWriteResGroup213 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
+  let Latency = 20;
+  let NumMicroOps = 5;
+  let ResourceCycles = [1,2,1,1];
+}
+def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPSYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPDYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPSYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDDYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDQYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQDYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQQYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDDYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQDYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDQYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQQYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPSYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPSYrm")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPDYrm")>;
+
+def SKLWriteResGroup215 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+  let Latency = 23;
+  let NumMicroOps = 3;
+  let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup215], (instregex "DIVR_FI16m")>;
+def: InstRW<[SKLWriteResGroup215], (instregex "DIVR_FI32m")>;
+
+def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
+  let Latency = 23;
+  let NumMicroOps = 8;
+  let ResourceCycles = [2,4,1,1];
+}
+def: InstRW<[SKLWriteResGroup217], (instregex "IDIV(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup217], (instregex "IDIV8m")>;
+
+def SKLWriteResGroup222 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
+  let Latency = 30;
+  let NumMicroOps = 23;
+  let ResourceCycles = [1,5,3,4,10];
+}
+def: InstRW<[SKLWriteResGroup222], (instregex "IN32ri")>;
+def: InstRW<[SKLWriteResGroup222], (instregex "IN32rr")>;
+def: InstRW<[SKLWriteResGroup222], (instregex "IN8ri")>;
+def: InstRW<[SKLWriteResGroup222], (instregex "IN8rr")>;
+
+def SKLWriteResGroup223 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 30;
+  let NumMicroOps = 23;
+  let ResourceCycles = [1,5,2,1,4,10];
+}
+def: InstRW<[SKLWriteResGroup223], (instregex "OUT32ir")>;
+def: InstRW<[SKLWriteResGroup223], (instregex "OUT32rr")>;
+def: InstRW<[SKLWriteResGroup223], (instregex "OUT8ir")>;
+def: InstRW<[SKLWriteResGroup223], (instregex "OUT8rr")>;
+
+def SKLWriteResGroup224 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
+  let Latency = 32;
+  let NumMicroOps = 31;
+  let ResourceCycles = [1,8,1,21];
+}
+def: InstRW<[SKLWriteResGroup224], (instregex "XRSTOR(64?)")>;
+
+def SKLWriteResGroup225 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
+  let Latency = 35;
+  let NumMicroOps = 18;
+  let ResourceCycles = [1,1,2,3,1,1,1,8];
+}
+def: InstRW<[SKLWriteResGroup225], (instregex "VMCLEARm")>;
+
+def SKLWriteResGroup226 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 36;
+  let NumMicroOps = 39;
+  let ResourceCycles = [1,10,1,1,26];
+}
+def: InstRW<[SKLWriteResGroup226], (instregex "XSAVE64")>;
+
+def SKLWriteResGroup231 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 37;
+  let NumMicroOps = 40;
+  let ResourceCycles = [1,11,1,1,26];
+}
+def: InstRW<[SKLWriteResGroup231], (instregex "XSAVE")>;
+
+def SKLWriteResGroup232 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+  let Latency = 41;
+  let NumMicroOps = 44;
+  let ResourceCycles = [1,11,1,1,30];
+}
+def: InstRW<[SKLWriteResGroup232], (instregex "XSAVEOPT")>;
+
+def SKLWriteResGroup233 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
+  let Latency = 42;
+  let NumMicroOps = 22;
+  let ResourceCycles = [2,20];
+}
+def: InstRW<[SKLWriteResGroup233], (instregex "RDTSCP")>;
+
+def SKLWriteResGroup234 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
+  let Latency = 57;
+  let NumMicroOps = 64;
+  let ResourceCycles = [2,8,5,10,39];
+}
+def: InstRW<[SKLWriteResGroup234], (instregex "FLDENVm")>;
+def: InstRW<[SKLWriteResGroup234], (instregex "FLDENVm")>;
+
+def SKLWriteResGroup235 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 58;
+  let NumMicroOps = 88;
+  let ResourceCycles = [4,4,31,1,2,1,45];
+}
+def: InstRW<[SKLWriteResGroup235], (instregex "FXRSTOR64")>;
+
+def SKLWriteResGroup236 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
+  let Latency = 58;
+  let NumMicroOps = 90;
+  let ResourceCycles = [4,2,33,1,2,1,47];
+}
+def: InstRW<[SKLWriteResGroup236], (instregex "FXRSTOR")>;
+
+def SKLWriteResGroup239 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
+  let Latency = 75;
+  let NumMicroOps = 15;
+  let ResourceCycles = [6,3,6];
+}
+def: InstRW<[SKLWriteResGroup239], (instregex "FNINIT")>;
+
+def SKLWriteResGroup240 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
+  let Latency = 76;
+  let NumMicroOps = 32;
+  let ResourceCycles = [7,2,8,3,1,11];
+}
+def: InstRW<[SKLWriteResGroup240], (instregex "DIV(16|32|64)r")>;
+
+def SKLWriteResGroup241 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
+  let Latency = 102;
+  let NumMicroOps = 66;
+  let ResourceCycles = [4,2,4,8,14,34];
+}
+def: InstRW<[SKLWriteResGroup241], (instregex "IDIV(16|32|64)r")>;
+
+def SKLWriteResGroup242 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
+  let Latency = 105;
+  let NumMicroOps = 100;
+  let ResourceCycles = [9,1,11,16,1,11,21,30];
+}
+def: InstRW<[SKLWriteResGroup242], (instregex "FSTENVm")>;
+def: InstRW<[SKLWriteResGroup242], (instregex "FSTENVm")>;
+
+} // SchedModel

Propchange: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
------------------------------------------------------------------------------
    svn:executable = *

Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Mon Sep 18 23:19:27 2017
@@ -666,4 +666,5 @@ include "X86SchedHaswell.td"
 include "X86ScheduleSLM.td"
 include "X86ScheduleZnver1.td"
 include "X86ScheduleBtVer2.td"
+include "X86SchedSkylakeClient.td"
 

Modified: llvm/trunk/test/CodeGen/X86/aes-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/aes-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/aes-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/aes-schedule.ll Mon Sep 18 23:19:27 2017
@@ -36,8 +36,8 @@ define <2 x i64> @test_aesdec(<2 x i64>
 ;
 ; SKYLAKE-LABEL: test_aesdec:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaesdec %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    vaesdec (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaesdec (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_aesdec:
@@ -85,8 +85,8 @@ define <2 x i64> @test_aesdeclast(<2 x i
 ;
 ; SKYLAKE-LABEL: test_aesdeclast:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_aesdeclast:
@@ -134,8 +134,8 @@ define <2 x i64> @test_aesenc(<2 x i64>
 ;
 ; SKYLAKE-LABEL: test_aesenc:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaesenc %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    vaesenc (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaesenc (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_aesenc:
@@ -183,8 +183,8 @@ define <2 x i64> @test_aesenclast(<2 x i
 ;
 ; SKYLAKE-LABEL: test_aesenclast:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaesenclast %xmm1, %xmm0, %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    vaesenclast (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaesenclast (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_aesenclast:
@@ -236,9 +236,9 @@ define <2 x i64> @test_aesimc(<2 x i64>
 ;
 ; SKYLAKE-LABEL: test_aesimc:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaesimc %xmm0, %xmm0 # sched: [14:2.00]
-; SKYLAKE-NEXT:    vaesimc (%rdi), %xmm1 # sched: [14:2.00]
-; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vaesimc %xmm0, %xmm0 # sched: [8:2.00]
+; SKYLAKE-NEXT:    vaesimc (%rdi), %xmm1 # sched: [8:2.00]
+; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_aesimc:
@@ -293,9 +293,9 @@ define <2 x i64> @test_aeskeygenassist(<
 ;
 ; SKYLAKE-LABEL: test_aeskeygenassist:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaeskeygenassist $7, %xmm0, %xmm0 # sched: [29:7.00]
-; SKYLAKE-NEXT:    vaeskeygenassist $7, (%rdi), %xmm1 # sched: [28:7.00]
-; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vaeskeygenassist $7, %xmm0, %xmm0 # sched: [20:6.00]
+; SKYLAKE-NEXT:    vaeskeygenassist $7, (%rdi), %xmm1 # sched: [19:6.00]
+; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_aeskeygenassist:

Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Mon Sep 18 23:19:27 2017
@@ -28,8 +28,8 @@ define <4 x double> @test_addpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_addpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addpd:
@@ -70,8 +70,8 @@ define <8 x float> @test_addps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_addps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addps:
@@ -112,8 +112,8 @@ define <4 x double> @test_addsubpd(<4 x
 ;
 ; SKYLAKE-LABEL: test_addsubpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddsubpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddsubpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addsubpd:
@@ -155,8 +155,8 @@ define <8 x float> @test_addsubps(<8 x f
 ;
 ; SKYLAKE-LABEL: test_addsubps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddsubps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddsubps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddsubps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddsubps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addsubps:
@@ -201,9 +201,9 @@ define <4 x double> @test_andnotpd(<4 x
 ;
 ; SKYLAKE-LABEL: test_andnotpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandnpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandnpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andnotpd:
@@ -256,9 +256,9 @@ define <8 x float> @test_andnotps(<8 x f
 ;
 ; SKYLAKE-LABEL: test_andnotps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandnps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandnps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vandnps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandnps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andnotps:
@@ -311,9 +311,9 @@ define <4 x double> @test_andpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_andpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vandpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andpd:
@@ -364,9 +364,9 @@ define <8 x float> @test_andps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_andps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vandps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andps:
@@ -417,8 +417,8 @@ define <4 x double> @test_blendpd(<4 x d
 ;
 ; SKYLAKE-LABEL: test_blendpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.33]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -463,7 +463,7 @@ define <8 x float> @test_blendps(<8 x fl
 ;
 ; SKYLAKE-LABEL: test_blendps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:0.33]
+; SKYLAKE-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:0.50]
 ; SKYLAKE-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -505,8 +505,8 @@ define <4 x double> @test_blendvpd(<4 x
 ;
 ; SKYLAKE-LABEL: test_blendvpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:2.00]
+; SKYLAKE-NEXT:    vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]
+; SKYLAKE-NEXT:    vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_blendvpd:
@@ -548,8 +548,8 @@ define <8 x float> @test_blendvps(<8 x f
 ;
 ; SKYLAKE-LABEL: test_blendvps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:2.00]
+; SKYLAKE-NEXT:    vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]
+; SKYLAKE-NEXT:    vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_blendvps:
@@ -737,9 +737,9 @@ define <4 x double> @test_cmppd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_cmppd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vorpd %ymm0, %ymm1, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cmppd:
@@ -789,9 +789,9 @@ define <8 x float> @test_cmpps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_cmpps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vorps %ymm0, %ymm1, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cmpps:
@@ -841,9 +841,9 @@ define <4 x double> @test_cvtdq2pd(<4 x
 ;
 ; SKYLAKE-LABEL: test_cvtdq2pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtdq2pd %xmm0, %ymm0 # sched: [6:1.00]
-; SKYLAKE-NEXT:    vcvtdq2pd (%rdi), %ymm1 # sched: [6:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtdq2pd %xmm0, %ymm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvtdq2pd (%rdi), %ymm1 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtdq2pd:
@@ -892,9 +892,9 @@ define <8 x float> @test_cvtdq2ps(<8 x i
 ;
 ; SKYLAKE-LABEL: test_cvtdq2ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtdq2ps %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcvtdq2ps (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtdq2ps %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcvtdq2ps (%rdi), %ymm1 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtdq2ps:
@@ -941,8 +941,8 @@ define <8 x i32> @test_cvtpd2dq(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_cvtpd2dq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttpd2dq %ymm0, %xmm0 # sched: [6:1.00]
-; SKYLAKE-NEXT:    vcvttpd2dqy (%rdi), %xmm1 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvttpd2dq %ymm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvttpd2dqy (%rdi), %xmm1 # sched: [8:1.00]
 ; SKYLAKE-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -990,8 +990,8 @@ define <8 x float> @test_cvtpd2ps(<4 x d
 ;
 ; SKYLAKE-LABEL: test_cvtpd2ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtpd2ps %ymm0, %xmm0 # sched: [6:1.00]
-; SKYLAKE-NEXT:    vcvtpd2psy (%rdi), %xmm1 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvtpd2ps %ymm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvtpd2psy (%rdi), %xmm1 # sched: [8:1.00]
 ; SKYLAKE-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1039,9 +1039,9 @@ define <8 x i32> @test_cvtps2dq(<8 x flo
 ;
 ; SKYLAKE-LABEL: test_cvtps2dq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttps2dq %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcvttps2dq (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vcvttps2dq %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcvttps2dq (%rdi), %ymm1 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtps2dq:
@@ -1085,8 +1085,8 @@ define <4 x double> @test_divpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_divpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdivpd %ymm1, %ymm0, %ymm0 # sched: [35:2.00]
-; SKYLAKE-NEXT:    vdivpd (%rdi), %ymm0, %ymm0 # sched: [35:2.00]
+; SKYLAKE-NEXT:    vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:1.00]
+; SKYLAKE-NEXT:    vdivpd (%rdi), %ymm0, %ymm0 # sched: [14:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_divpd:
@@ -1127,8 +1127,8 @@ define <8 x float> @test_divps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_divps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdivps %ymm1, %ymm0, %ymm0 # sched: [21:2.00]
-; SKYLAKE-NEXT:    vdivps (%rdi), %ymm0, %ymm0 # sched: [21:2.00]
+; SKYLAKE-NEXT:    vdivps %ymm1, %ymm0, %ymm0 # sched: [11:1.00]
+; SKYLAKE-NEXT:    vdivps (%rdi), %ymm0, %ymm0 # sched: [11:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_divps:
@@ -1169,8 +1169,8 @@ define <8 x float> @test_dpps(<8 x float
 ;
 ; SKYLAKE-LABEL: test_dpps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [14:2.00]
-; SKYLAKE-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [14:2.00]
+; SKYLAKE-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [13:1.33]
+; SKYLAKE-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [13:1.33]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_dpps:
@@ -1259,8 +1259,8 @@ define <4 x double> @test_haddpd(<4 x do
 ;
 ; SKYLAKE-LABEL: test_haddpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_haddpd:
@@ -1302,8 +1302,8 @@ define <8 x float> @test_haddps(<8 x flo
 ;
 ; SKYLAKE-LABEL: test_haddps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_haddps:
@@ -1345,8 +1345,8 @@ define <4 x double> @test_hsubpd(<4 x do
 ;
 ; SKYLAKE-LABEL: test_hsubpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_hsubpd:
@@ -1388,8 +1388,8 @@ define <8 x float> @test_hsubps(<8 x flo
 ;
 ; SKYLAKE-LABEL: test_hsubps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_hsubps:
@@ -1436,7 +1436,7 @@ define <8 x float> @test_insertf128(<8 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_insertf128:
@@ -1520,8 +1520,8 @@ define <2 x double> @test_maskmovpd(i8*
 ;
 ; SKYLAKE-LABEL: test_maskmovpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovapd %xmm2, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1569,8 +1569,8 @@ define <4 x double> @test_maskmovpd_ymm(
 ;
 ; SKYLAKE-LABEL: test_maskmovpd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovapd %ymm2, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1618,8 +1618,8 @@ define <4 x float> @test_maskmovps(i8* %
 ;
 ; SKYLAKE-LABEL: test_maskmovps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovaps %xmm2, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1667,8 +1667,8 @@ define <8 x float> @test_maskmovps_ymm(i
 ;
 ; SKYLAKE-LABEL: test_maskmovps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovaps %ymm2, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1713,8 +1713,8 @@ define <4 x double> @test_maxpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_maxpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vmaxpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vmaxpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_maxpd:
@@ -1756,8 +1756,8 @@ define <8 x float> @test_maxps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_maxps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaxps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vmaxps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmaxps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vmaxps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_maxps:
@@ -1799,8 +1799,8 @@ define <4 x double> @test_minpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_minpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vminpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vminpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vminpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vminpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_minpd:
@@ -1842,8 +1842,8 @@ define <8 x float> @test_minps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_minps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vminps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vminps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vminps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vminps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_minps:
@@ -1889,7 +1889,7 @@ define <4 x double> @test_movapd(<4 x do
 ; SKYLAKE-LABEL: test_movapd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovapd (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovapd %ymm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1937,7 +1937,7 @@ define <8 x float> @test_movaps(<8 x flo
 ; SKYLAKE-LABEL: test_movaps:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovaps (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovaps %ymm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1986,7 +1986,7 @@ define <4 x double> @test_movddup(<4 x d
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movddup:
@@ -2030,7 +2030,7 @@ define i32 @test_movmskpd(<4 x double> %
 ;
 ; SKYLAKE-LABEL: test_movmskpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmovmskpd %ymm0, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmovmskpd %ymm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2070,7 +2070,7 @@ define i32 @test_movmskps(<8 x float> %a
 ;
 ; SKYLAKE-LABEL: test_movmskps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmovmskps %ymm0, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmovmskps %ymm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2110,7 +2110,7 @@ define <4 x double> @test_movntpd(<4 x d
 ;
 ; SKYLAKE-LABEL: test_movntpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovntpd %ymm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2151,7 +2151,7 @@ define <8 x float> @test_movntps(<8 x fl
 ;
 ; SKYLAKE-LABEL: test_movntps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovntps %ymm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2197,7 +2197,7 @@ define <8 x float> @test_movshdup(<8 x f
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movshdup:
@@ -2246,7 +2246,7 @@ define <8 x float> @test_movsldup(<8 x f
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movsldup:
@@ -2296,7 +2296,7 @@ define <4 x double> @test_movupd(<4 x do
 ; SKYLAKE-LABEL: test_movupd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovupd (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovupd %ymm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2346,7 +2346,7 @@ define <8 x float> @test_movups(<8 x flo
 ; SKYLAKE-LABEL: test_movups:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovups (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovups %ymm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2390,8 +2390,8 @@ define <4 x double> @test_mulpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_mulpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmulpd %ymm1, %ymm0, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vmulpd (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vmulpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vmulpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mulpd:
@@ -2432,8 +2432,8 @@ define <8 x float> @test_mulps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_mulps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmulps %ymm1, %ymm0, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vmulps (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vmulps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vmulps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mulps:
@@ -2477,9 +2477,9 @@ define <4 x double> @orpd(<4 x double> %
 ;
 ; SKYLAKE-LABEL: orpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vorpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vorpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vorpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: orpd:
@@ -2530,9 +2530,9 @@ define <8 x float> @test_orps(<8 x float
 ;
 ; SKYLAKE-LABEL: test_orps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vorps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vorps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_orps:
@@ -2585,7 +2585,7 @@ define <4 x double> @test_perm2f128(<4 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]
 ; SKYLAKE-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_perm2f128:
@@ -2634,7 +2634,7 @@ define <2 x double> @test_permilpd(<2 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_permilpd:
@@ -2683,7 +2683,7 @@ define <4 x double> @test_permilpd_ymm(<
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_permilpd_ymm:
@@ -2732,7 +2732,7 @@ define <4 x float> @test_permilps(<4 x f
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_permilps:
@@ -2781,7 +2781,7 @@ define <8 x float> @test_permilps_ymm(<8
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_permilps_ymm:
@@ -3000,9 +3000,9 @@ define <8 x float> @test_rcpps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_rcpps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vrcpps (%rdi), %ymm1 # sched: [11:2.00]
-; SKYLAKE-NEXT:    vrcpps %ymm0, %ymm0 # sched: [11:2.00]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vrcpps %ymm0, %ymm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vrcpps (%rdi), %ymm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_rcpps:
@@ -3050,9 +3050,9 @@ define <4 x double> @test_roundpd(<4 x d
 ;
 ; SKYLAKE-LABEL: test_roundpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vroundpd $7, %ymm0, %ymm0 # sched: [5:1.25]
-; SKYLAKE-NEXT:    vroundpd $7, (%rdi), %ymm1 # sched: [6:2.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vroundpd $7, %ymm0, %ymm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vroundpd $7, (%rdi), %ymm1 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_roundpd:
@@ -3100,9 +3100,9 @@ define <8 x float> @test_roundps(<8 x fl
 ;
 ; SKYLAKE-LABEL: test_roundps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vroundps $7, %ymm0, %ymm0 # sched: [5:1.25]
-; SKYLAKE-NEXT:    vroundps $7, (%rdi), %ymm1 # sched: [6:2.00]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vroundps $7, %ymm0, %ymm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vroundps $7, (%rdi), %ymm1 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_roundps:
@@ -3150,9 +3150,9 @@ define <8 x float> @test_rsqrtps(<8 x fl
 ;
 ; SKYLAKE-LABEL: test_rsqrtps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vrsqrtps (%rdi), %ymm1 # sched: [11:2.00]
-; SKYLAKE-NEXT:    vrsqrtps %ymm0, %ymm0 # sched: [11:2.00]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vrsqrtps %ymm0, %ymm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vrsqrtps (%rdi), %ymm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_rsqrtps:
@@ -3202,7 +3202,7 @@ define <4 x double> @test_shufpd(<4 x do
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[2],ymm1[3] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_shufpd:
@@ -3291,9 +3291,9 @@ define <4 x double> @test_sqrtpd(<4 x do
 ;
 ; SKYLAKE-LABEL: test_sqrtpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsqrtpd (%rdi), %ymm1 # sched: [35:2.00]
-; SKYLAKE-NEXT:    vsqrtpd %ymm0, %ymm0 # sched: [35:2.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsqrtpd %ymm0, %ymm0 # sched: [18:1.00]
+; SKYLAKE-NEXT:    vsqrtpd (%rdi), %ymm1 # sched: [18:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_sqrtpd:
@@ -3341,9 +3341,9 @@ define <8 x float> @test_sqrtps(<8 x flo
 ;
 ; SKYLAKE-LABEL: test_sqrtps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsqrtps (%rdi), %ymm1 # sched: [21:2.00]
-; SKYLAKE-NEXT:    vsqrtps %ymm0, %ymm0 # sched: [21:2.00]
-; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsqrtps %ymm0, %ymm0 # sched: [12:1.00]
+; SKYLAKE-NEXT:    vsqrtps (%rdi), %ymm1 # sched: [12:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_sqrtps:
@@ -3388,8 +3388,8 @@ define <4 x double> @test_subpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_subpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsubpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vsubpd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsubpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vsubpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_subpd:
@@ -3430,8 +3430,8 @@ define <8 x float> @test_subps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_subps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsubps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vsubps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsubps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vsubps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_subps:
@@ -3482,10 +3482,10 @@ define i32 @test_testpd(<2 x double> %a0
 ; SKYLAKE-LABEL: test_testpd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    xorl %eax, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT:    vtestpd %xmm1, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    setb %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    vtestpd (%rdi), %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    adcl $0, %eax # sched: [2:0.50]
+; SKYLAKE-NEXT:    vtestpd %xmm1, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    setb %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    vtestpd (%rdi), %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    adcl $0, %eax # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_testpd:
@@ -3547,10 +3547,10 @@ define i32 @test_testpd_ymm(<4 x double>
 ; SKYLAKE-LABEL: test_testpd_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    xorl %eax, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT:    vtestpd %ymm1, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    setb %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    vtestpd (%rdi), %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    adcl $0, %eax # sched: [2:0.50]
+; SKYLAKE-NEXT:    vtestpd %ymm1, %ymm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    setb %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    vtestpd (%rdi), %ymm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    adcl $0, %eax # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3611,10 +3611,10 @@ define i32 @test_testps(<4 x float> %a0,
 ; SKYLAKE-LABEL: test_testps:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    xorl %eax, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT:    vtestps %xmm1, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    setb %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    vtestps (%rdi), %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    adcl $0, %eax # sched: [2:0.50]
+; SKYLAKE-NEXT:    vtestps %xmm1, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    setb %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    vtestps (%rdi), %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    adcl $0, %eax # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_testps:
@@ -3676,10 +3676,10 @@ define i32 @test_testps_ymm(<8 x float>
 ; SKYLAKE-LABEL: test_testps_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    xorl %eax, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT:    vtestps %ymm1, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    setb %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    vtestps (%rdi), %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    adcl $0, %eax # sched: [2:0.50]
+; SKYLAKE-NEXT:    vtestps %ymm1, %ymm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    setb %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    vtestps (%rdi), %ymm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    adcl $0, %eax # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3735,7 +3735,7 @@ define <4 x double> @test_unpckhpd(<4 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_unpckhpd:
@@ -3826,7 +3826,7 @@ define <4 x double> @test_unpcklpd(<4 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_unpcklpd:
@@ -3915,9 +3915,9 @@ define <4 x double> @test_xorpd(<4 x dou
 ;
 ; SKYLAKE-LABEL: test_xorpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vxorpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vxorpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_xorpd:
@@ -3968,9 +3968,9 @@ define <8 x float> @test_xorps(<8 x floa
 ;
 ; SKYLAKE-LABEL: test_xorps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vxorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vxorps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vxorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vxorps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_xorps:
@@ -4015,7 +4015,7 @@ define void @test_zeroall() {
 ;
 ; SKYLAKE-LABEL: test_zeroall:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vzeroall # sched: [16:16.00]
+; SKYLAKE-NEXT:    vzeroall # sched: [16:4.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_zeroall:

Modified: llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-schedule.ll Mon Sep 18 23:19:27 2017
@@ -50,7 +50,7 @@ define <4 x double> @test_broadcastsd_ym
 ; SKYLAKE-LABEL: test_broadcastsd_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vbroadcastsd %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_broadcastsd_ymm:
@@ -79,7 +79,7 @@ define <4 x float> @test_broadcastss(<4
 ; SKYLAKE-LABEL: test_broadcastss:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vbroadcastss %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_broadcastss:
@@ -108,7 +108,7 @@ define <8 x float> @test_broadcastss_ymm
 ; SKYLAKE-LABEL: test_broadcastss_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vbroadcastss %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_broadcastss_ymm:
@@ -178,7 +178,7 @@ define <2 x double> @test_gatherdpd(<2 x
 ;
 ; SKYLAKE-LABEL: test_gatherdpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdpd:
@@ -203,7 +203,7 @@ define <4 x double> @test_gatherdpd_ymm(
 ;
 ; SKYLAKE-LABEL: test_gatherdpd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdpd_ymm:
@@ -228,7 +228,7 @@ define <4 x float> @test_gatherdps(<4 x
 ;
 ; SKYLAKE-LABEL: test_gatherdps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdps:
@@ -253,7 +253,7 @@ define <8 x float> @test_gatherdps_ymm(<
 ;
 ; SKYLAKE-LABEL: test_gatherdps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherdps_ymm:
@@ -278,7 +278,7 @@ define <2 x double> @test_gatherqpd(<2 x
 ;
 ; SKYLAKE-LABEL: test_gatherqpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqpd:
@@ -303,7 +303,7 @@ define <4 x double> @test_gatherqpd_ymm(
 ;
 ; SKYLAKE-LABEL: test_gatherqpd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqpd_ymm:
@@ -328,7 +328,7 @@ define <4 x float> @test_gatherqps(<4 x
 ;
 ; SKYLAKE-LABEL: test_gatherqps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_gatherqps:
@@ -355,7 +355,7 @@ define <4 x float> @test_gatherqps_ymm(<
 ;
 ; SKYLAKE-LABEL: test_gatherqps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -446,8 +446,8 @@ define <16 x i16> @test_mpsadbw(<32 x i8
 ;
 ; SKYLAKE-LABEL: test_mpsadbw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [7:2.00]
-; SKYLAKE-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [7:2.00]
+; SKYLAKE-NEXT:    vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
+; SKYLAKE-NEXT:    vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [4:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_mpsadbw:
@@ -480,9 +480,9 @@ define <32 x i8> @test_pabsb(<32 x i8> %
 ;
 ; SKYLAKE-LABEL: test_pabsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpabsb %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpabsb %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpabsb (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pabsb:
@@ -516,9 +516,9 @@ define <8 x i32> @test_pabsd(<8 x i32> %
 ;
 ; SKYLAKE-LABEL: test_pabsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpabsd %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpabsd %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpabsd (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pabsd:
@@ -552,9 +552,9 @@ define <16 x i16> @test_pabsw(<16 x i16>
 ;
 ; SKYLAKE-LABEL: test_pabsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpabsw %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpabsw %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpabsw (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pabsw:
@@ -804,7 +804,7 @@ define <32 x i8> @test_paddsb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_paddsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -835,7 +835,7 @@ define <16 x i16> @test_paddsw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_paddsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -866,7 +866,7 @@ define <32 x i8> @test_paddusb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_paddusb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -897,7 +897,7 @@ define <16 x i16> @test_paddusw(<16 x i1
 ;
 ; SKYLAKE-LABEL: test_paddusw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -990,7 +990,7 @@ define <4 x i64> @test_pand(<4 x i64> %a
 ;
 ; SKYLAKE-LABEL: test_pand:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpand (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -1025,7 +1025,7 @@ define <4 x i64> @test_pandn(<4 x i64> %
 ;
 ; SKYLAKE-LABEL: test_pandn:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpandn (%rdi), %ymm0, %ymm1 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -1060,7 +1060,7 @@ define <32 x i8> @test_pavgb(<32 x i8> %
 ;
 ; SKYLAKE-LABEL: test_pavgb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpavgb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1100,7 +1100,7 @@ define <16 x i16> @test_pavgw(<16 x i16>
 ;
 ; SKYLAKE-LABEL: test_pavgw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpavgw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1142,7 +1142,7 @@ define <4 x i32> @test_pblendd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pblendd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.33]
+; SKYLAKE-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -1177,7 +1177,7 @@ define <8 x i32> @test_pblendd_ymm(<8 x
 ;
 ; SKYLAKE-LABEL: test_pblendd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],ymm1[7] sched: [1:0.33]
+; SKYLAKE-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],ymm1[7] sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,7] sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -1210,8 +1210,8 @@ define <32 x i8> @test_pblendvb(<32 x i8
 ;
 ; SKYLAKE-LABEL: test_pblendvb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [2:2.00]
+; SKYLAKE-NEXT:    vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]
+; SKYLAKE-NEXT:    vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pblendvb:
@@ -1242,7 +1242,7 @@ define <16 x i16> @test_pblendw(<16 x i1
 ; SKYLAKE-LABEL: test_pblendw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4],ymm0[5,6,7,8,9],ymm1[10,11,12],ymm0[13,14,15] sched: [1:1.00]
-; SKYLAKE-NEXT:    vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7],mem[8],ymm0[9],mem[10],ymm0[11],mem[12],ymm0[13],mem[14],ymm0[15] sched: [4:1.00]
+; SKYLAKE-NEXT:    vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7],mem[8],ymm0[9],mem[10],ymm0[11],mem[12],ymm0[13],mem[14],ymm0[15] sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pblendw:
@@ -1274,7 +1274,7 @@ define <16 x i8> @test_pbroadcastb(<16 x
 ; SKYLAKE-LABEL: test_pbroadcastb:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpbroadcastb %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vpbroadcastb (%rdi), %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpbroadcastb (%rdi), %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1309,7 +1309,7 @@ define <32 x i8> @test_pbroadcastb_ymm(<
 ; SKYLAKE-LABEL: test_pbroadcastb_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpbroadcastb %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vpbroadcastb (%rdi), %ymm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpbroadcastb (%rdi), %ymm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1484,7 +1484,7 @@ define <8 x i16> @test_pbroadcastw(<8 x
 ; SKYLAKE-LABEL: test_pbroadcastw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpbroadcastw %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vpbroadcastw (%rdi), %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpbroadcastw (%rdi), %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1519,7 +1519,7 @@ define <16 x i16> @test_pbroadcastw_ymm(
 ; SKYLAKE-LABEL: test_pbroadcastw_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpbroadcastw %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vpbroadcastw (%rdi), %ymm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpbroadcastw (%rdi), %ymm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1551,7 +1551,7 @@ define <32 x i8> @test_pcmpeqb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1583,7 +1583,7 @@ define <8 x i32> @test_pcmpeqd(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1615,7 +1615,7 @@ define <4 x i64> @test_pcmpeqq(<4 x i64>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1647,7 +1647,7 @@ define <16 x i16> @test_pcmpeqw(<16 x i1
 ;
 ; SKYLAKE-LABEL: test_pcmpeqw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1679,7 +1679,7 @@ define <32 x i8> @test_pcmpgtb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1711,7 +1711,7 @@ define <8 x i32> @test_pcmpgtd(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1743,8 +1743,8 @@ define <4 x i64> @test_pcmpgtq(<4 x i64>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pcmpgtq:
@@ -1775,7 +1775,7 @@ define <16 x i16> @test_pcmpgtw(<16 x i1
 ;
 ; SKYLAKE-LABEL: test_pcmpgtw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1882,7 +1882,7 @@ define <4 x double> @test_permpd(<4 x do
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_permpd:
@@ -1917,7 +1917,7 @@ define <8 x float> @test_permps(<8 x i32
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpermps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpermps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_permps:
@@ -1982,7 +1982,7 @@ define <4 x i32> @test_pgatherdd(<4 x i3
 ;
 ; SKYLAKE-LABEL: test_pgatherdd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdd:
@@ -2007,7 +2007,7 @@ define <8 x i32> @test_pgatherdd_ymm(<8
 ;
 ; SKYLAKE-LABEL: test_pgatherdd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdd_ymm:
@@ -2032,7 +2032,7 @@ define <2 x i64> @test_pgatherdq(<2 x i6
 ;
 ; SKYLAKE-LABEL: test_pgatherdq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdq:
@@ -2057,7 +2057,7 @@ define <4 x i64> @test_pgatherdq_ymm(<4
 ;
 ; SKYLAKE-LABEL: test_pgatherdq_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherdq_ymm:
@@ -2082,7 +2082,7 @@ define <4 x i32> @test_pgatherqd(<4 x i3
 ;
 ; SKYLAKE-LABEL: test_pgatherqd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqd:
@@ -2109,7 +2109,7 @@ define <4 x i32> @test_pgatherqd_ymm(<4
 ;
 ; SKYLAKE-LABEL: test_pgatherqd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2136,7 +2136,7 @@ define <2 x i64> @test_pgatherqq(<2 x i6
 ;
 ; SKYLAKE-LABEL: test_pgatherqq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqq:
@@ -2161,7 +2161,7 @@ define <4 x i64> @test_pgatherqq_ymm(<4
 ;
 ; SKYLAKE-LABEL: test_pgatherqq_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [1:?]
+; SKYLAKE-NEXT:    vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [20:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pgatherqq_ymm:
@@ -2374,8 +2374,8 @@ define <16 x i16> @test_pmaddubsw(<32 x
 ;
 ; SKYLAKE-LABEL: test_pmaddubsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmaddubsw:
@@ -2406,8 +2406,8 @@ define <8 x i32> @test_pmaddwd(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pmaddwd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmaddwd:
@@ -2440,8 +2440,8 @@ define <4 x i32> @test_pmaskmovd(i8* %a0
 ;
 ; SKYLAKE-LABEL: test_pmaskmovd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2475,8 +2475,8 @@ define <8 x i32> @test_pmaskmovd_ymm(i8*
 ;
 ; SKYLAKE-LABEL: test_pmaskmovd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2510,8 +2510,8 @@ define <2 x i64> @test_pmaskmovq(i8* %a0
 ;
 ; SKYLAKE-LABEL: test_pmaskmovq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2545,8 +2545,8 @@ define <4 x i64> @test_pmaskmovq_ymm(i8*
 ;
 ; SKYLAKE-LABEL: test_pmaskmovq_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2578,7 +2578,7 @@ define <32 x i8> @test_pmaxsb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_pmaxsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2609,7 +2609,7 @@ define <8 x i32> @test_pmaxsd(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmaxsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2640,7 +2640,7 @@ define <16 x i16> @test_pmaxsw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pmaxsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2671,7 +2671,7 @@ define <32 x i8> @test_pmaxub(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_pmaxub:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2702,7 +2702,7 @@ define <8 x i32> @test_pmaxud(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmaxud:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2733,7 +2733,7 @@ define <16 x i16> @test_pmaxuw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pmaxuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2764,7 +2764,7 @@ define <32 x i8> @test_pminsb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_pminsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2795,7 +2795,7 @@ define <8 x i32> @test_pminsd(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pminsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2826,7 +2826,7 @@ define <16 x i16> @test_pminsw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pminsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2857,7 +2857,7 @@ define <32 x i8> @test_pminub(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_pminub:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminub %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2888,7 +2888,7 @@ define <8 x i32> @test_pminud(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pminud:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminud %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2919,7 +2919,7 @@ define <16 x i16> @test_pminuw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pminuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2950,7 +2950,7 @@ define i32 @test_pmovmskb(<32 x i8> %a0)
 ;
 ; SKYLAKE-LABEL: test_pmovmskb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmovmskb %ymm0, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3411,8 +3411,8 @@ define <4 x i64> @test_pmuldq(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmuldq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmuldq %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmuldq (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmuldq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmuldq (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmuldq:
@@ -3443,8 +3443,8 @@ define <16 x i16> @test_pmulhrsw(<16 x i
 ;
 ; SKYLAKE-LABEL: test_pmulhrsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmulhrsw:
@@ -3474,8 +3474,8 @@ define <16 x i16> @test_pmulhuw(<16 x i1
 ;
 ; SKYLAKE-LABEL: test_pmulhuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmulhuw:
@@ -3505,8 +3505,8 @@ define <16 x i16> @test_pmulhw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pmulhw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulhw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmulhw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmulhw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmulhw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmulhw:
@@ -3536,8 +3536,8 @@ define <8 x i32> @test_pmulld(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmulld:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 # sched: [10:2.00]
-; SKYLAKE-NEXT:    vpmulld (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vpmulld (%rdi), %ymm0, %ymm0 # sched: [8:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmulld:
@@ -3566,8 +3566,8 @@ define <16 x i16> @test_pmullw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_pmullw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmullw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmullw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmullw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmullw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmullw:
@@ -3596,8 +3596,8 @@ define <4 x i64> @test_pmuludq(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmuludq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmuludq %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmuludq (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmuludq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmuludq (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pmuludq:
@@ -3630,7 +3630,7 @@ define <4 x i64> @test_por(<4 x i64> %a0
 ;
 ; SKYLAKE-LABEL: test_por:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -3663,8 +3663,8 @@ define <4 x i64> @test_psadbw(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_psadbw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsadbw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpsadbw (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpsadbw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vpsadbw (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psadbw:
@@ -3765,7 +3765,7 @@ define <16 x i16> @test_pshufhw(<16 x i1
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,5,4,8,9,10,11,15,14,13,12] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,13,12,15,14] sched: [1:1.00]
-; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pshufhw:
@@ -3800,7 +3800,7 @@ define <16 x i16> @test_pshuflw(<16 x i1
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7,11,10,9,8,12,13,14,15] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15] sched: [1:1.00]
-; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_pshuflw:
@@ -3831,7 +3831,7 @@ define <32 x i8> @test_psignb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_psignb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsignb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3862,7 +3862,7 @@ define <8 x i32> @test_psignd(<8 x i32>
 ;
 ; SKYLAKE-LABEL: test_psignd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsignd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3893,7 +3893,7 @@ define <16 x i16> @test_psignw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_psignw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsignw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3927,7 +3927,7 @@ define <8 x i32> @test_pslld(<8 x i32> %
 ; SKYLAKE-LABEL: test_pslld:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpslld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpslld (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpslld (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpslld $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3987,7 +3987,7 @@ define <4 x i64> @test_psllq(<4 x i64> %
 ; SKYLAKE-LABEL: test_psllq:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsllq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsllq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsllq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsllq $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4020,8 +4020,8 @@ define <4 x i32> @test_psllvd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_psllvd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsllvd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT:    vpsllvd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
+; SKYLAKE-NEXT:    vpsllvd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsllvd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psllvd:
@@ -4051,8 +4051,8 @@ define <8 x i32> @test_psllvd_ymm(<8 x i
 ;
 ; SKYLAKE-LABEL: test_psllvd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT:    vpsllvd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
+; SKYLAKE-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsllvd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psllvd_ymm:
@@ -4083,7 +4083,7 @@ define <2 x i64> @test_psllvq(<2 x i64>
 ; SKYLAKE-LABEL: test_psllvq:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsllvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vpsllvq (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsllvq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psllvq:
@@ -4114,7 +4114,7 @@ define <4 x i64> @test_psllvq_ymm(<4 x i
 ; SKYLAKE-LABEL: test_psllvq_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsllvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vpsllvq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsllvq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psllvq_ymm:
@@ -4147,7 +4147,7 @@ define <16 x i16> @test_psllw(<16 x i16>
 ; SKYLAKE-LABEL: test_psllw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsllw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsllw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsllw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsllw $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4183,7 +4183,7 @@ define <8 x i32> @test_psrad(<8 x i32> %
 ; SKYLAKE-LABEL: test_psrad:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrad %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsrad (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrad (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrad $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4216,8 +4216,8 @@ define <4 x i32> @test_psravd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_psravd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsravd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT:    vpsravd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
+; SKYLAKE-NEXT:    vpsravd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsravd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psravd:
@@ -4247,8 +4247,8 @@ define <8 x i32> @test_psravd_ymm(<8 x i
 ;
 ; SKYLAKE-LABEL: test_psravd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsravd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT:    vpsravd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
+; SKYLAKE-NEXT:    vpsravd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsravd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psravd_ymm:
@@ -4281,7 +4281,7 @@ define <16 x i16> @test_psraw(<16 x i16>
 ; SKYLAKE-LABEL: test_psraw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsraw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsraw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsraw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsraw $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4317,7 +4317,7 @@ define <8 x i32> @test_psrld(<8 x i32> %
 ; SKYLAKE-LABEL: test_psrld:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsrld (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrld (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrld $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4377,7 +4377,7 @@ define <4 x i64> @test_psrlq(<4 x i64> %
 ; SKYLAKE-LABEL: test_psrlq:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrlq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsrlq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrlq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrlq $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4410,8 +4410,8 @@ define <4 x i32> @test_psrlvd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_psrlvd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT:    vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
+; SKYLAKE-NEXT:    vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psrlvd:
@@ -4441,8 +4441,8 @@ define <8 x i32> @test_psrlvd_ymm(<8 x i
 ;
 ; SKYLAKE-LABEL: test_psrlvd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT:    vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
+; SKYLAKE-NEXT:    vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psrlvd_ymm:
@@ -4473,7 +4473,7 @@ define <2 x i64> @test_psrlvq(<2 x i64>
 ; SKYLAKE-LABEL: test_psrlvq:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrlvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psrlvq:
@@ -4504,7 +4504,7 @@ define <4 x i64> @test_psrlvq_ymm(<4 x i
 ; SKYLAKE-LABEL: test_psrlvq_ymm:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrlvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_psrlvq_ymm:
@@ -4537,7 +4537,7 @@ define <16 x i16> @test_psrlw(<16 x i16>
 ; SKYLAKE-LABEL: test_psrlw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrlw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vpsrlw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vpsrlw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrlw $2, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4660,7 +4660,7 @@ define <32 x i8> @test_psubsb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_psubsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4691,7 +4691,7 @@ define <16 x i16> @test_psubsw(<16 x i16
 ;
 ; SKYLAKE-LABEL: test_psubsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4722,7 +4722,7 @@ define <32 x i8> @test_psubusb(<32 x i8>
 ;
 ; SKYLAKE-LABEL: test_psubusb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4753,7 +4753,7 @@ define <16 x i16> @test_psubusw(<16 x i1
 ;
 ; SKYLAKE-LABEL: test_psubusw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4850,7 +4850,7 @@ define <8 x i32> @test_punpckhdq(<8 x i3
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpunpckhdq {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]
-; SKYLAKE-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4984,7 +4984,7 @@ define <8 x i32> @test_punpckldq(<8 x i3
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]
-; SKYLAKE-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5084,7 +5084,7 @@ define <4 x i64> @test_pxor(<4 x i64> %a
 ;
 ; SKYLAKE-LABEL: test_pxor:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpxor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]

Modified: llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll Mon Sep 18 23:19:27 2017
@@ -230,12 +230,26 @@ define i32 @test_rorx_i32(i32 %a0, i32 %
 ; GENERIC-NEXT:    addl %ecx, %eax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_rorx_i32:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    rorxl $5, %edi, %ecx # sched: [1:0.50]
-; COMMON-NEXT:    rorxl $5, (%rdx), %eax # sched: [1:0.50]
-; COMMON-NEXT:    addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_rorx_i32:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    rorxl $5, %edi, %ecx # sched: [1:0.50]
+; HASWELL-NEXT:    rorxl $5, (%rdx), %eax # sched: [1:0.50]
+; HASWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_rorx_i32:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    rorxl $5, %edi, %ecx # sched: [1:1.00]
+; SKYLAKE-NEXT:    rorxl $5, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_rorx_i32:
+; KNL:       # BB#0:
+; KNL-NEXT:    rorxl $5, %edi, %ecx # sched: [1:0.50]
+; KNL-NEXT:    rorxl $5, (%rdx), %eax # sched: [1:0.50]
+; KNL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_rorx_i32:
 ; ZNVER1:       # BB#0:
@@ -262,12 +276,26 @@ define i64 @test_rorx_i64(i64 %a0, i64 %
 ; GENERIC-NEXT:    addq %rcx, %rax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_rorx_i64:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    rorxq $5, %rdi, %rcx # sched: [1:0.50]
-; COMMON-NEXT:    rorxq $5, (%rdx), %rax # sched: [1:0.50]
-; COMMON-NEXT:    addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_rorx_i64:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    rorxq $5, %rdi, %rcx # sched: [1:0.50]
+; HASWELL-NEXT:    rorxq $5, (%rdx), %rax # sched: [1:0.50]
+; HASWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_rorx_i64:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    rorxq $5, %rdi, %rcx # sched: [1:1.00]
+; SKYLAKE-NEXT:    rorxq $5, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_rorx_i64:
+; KNL:       # BB#0:
+; KNL-NEXT:    rorxq $5, %rdi, %rcx # sched: [1:0.50]
+; KNL-NEXT:    rorxq $5, (%rdx), %rax # sched: [1:0.50]
+; KNL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_rorx_i64:
 ; ZNVER1:       # BB#0:
@@ -294,12 +322,26 @@ define i32 @test_sarx_i32(i32 %a0, i32 %
 ; GENERIC-NEXT:    addl %ecx, %eax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_sarx_i32:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    sarxl %esi, %edi, %ecx # sched: [1:0.50]
-; COMMON-NEXT:    sarxl %esi, (%rdx), %eax # sched: [1:0.50]
-; COMMON-NEXT:    addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_sarx_i32:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    sarxl %esi, %edi, %ecx # sched: [1:0.50]
+; HASWELL-NEXT:    sarxl %esi, (%rdx), %eax # sched: [1:0.50]
+; HASWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_sarx_i32:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    sarxl %esi, %edi, %ecx # sched: [1:1.00]
+; SKYLAKE-NEXT:    sarxl %esi, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_sarx_i32:
+; KNL:       # BB#0:
+; KNL-NEXT:    sarxl %esi, %edi, %ecx # sched: [1:0.50]
+; KNL-NEXT:    sarxl %esi, (%rdx), %eax # sched: [1:0.50]
+; KNL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_sarx_i32:
 ; ZNVER1:       # BB#0:
@@ -322,12 +364,26 @@ define i64 @test_sarx_i64(i64 %a0, i64 %
 ; GENERIC-NEXT:    addq %rcx, %rax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_sarx_i64:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    sarxq %rsi, %rdi, %rcx # sched: [1:0.50]
-; COMMON-NEXT:    sarxq %rsi, (%rdx), %rax # sched: [1:0.50]
-; COMMON-NEXT:    addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_sarx_i64:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    sarxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; HASWELL-NEXT:    sarxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; HASWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_sarx_i64:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    sarxq %rsi, %rdi, %rcx # sched: [1:1.00]
+; SKYLAKE-NEXT:    sarxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_sarx_i64:
+; KNL:       # BB#0:
+; KNL-NEXT:    sarxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; KNL-NEXT:    sarxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; KNL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_sarx_i64:
 ; ZNVER1:       # BB#0:
@@ -350,12 +406,26 @@ define i32 @test_shlx_i32(i32 %a0, i32 %
 ; GENERIC-NEXT:    addl %ecx, %eax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_shlx_i32:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    shlxl %esi, %edi, %ecx # sched: [1:0.50]
-; COMMON-NEXT:    shlxl %esi, (%rdx), %eax # sched: [1:0.50]
-; COMMON-NEXT:    addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_shlx_i32:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    shlxl %esi, %edi, %ecx # sched: [1:0.50]
+; HASWELL-NEXT:    shlxl %esi, (%rdx), %eax # sched: [1:0.50]
+; HASWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_shlx_i32:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    shlxl %esi, %edi, %ecx # sched: [1:1.00]
+; SKYLAKE-NEXT:    shlxl %esi, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_shlx_i32:
+; KNL:       # BB#0:
+; KNL-NEXT:    shlxl %esi, %edi, %ecx # sched: [1:0.50]
+; KNL-NEXT:    shlxl %esi, (%rdx), %eax # sched: [1:0.50]
+; KNL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_shlx_i32:
 ; ZNVER1:       # BB#0:
@@ -378,12 +448,26 @@ define i64 @test_shlx_i64(i64 %a0, i64 %
 ; GENERIC-NEXT:    addq %rcx, %rax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_shlx_i64:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    shlxq %rsi, %rdi, %rcx # sched: [1:0.50]
-; COMMON-NEXT:    shlxq %rsi, (%rdx), %rax # sched: [1:0.50]
-; COMMON-NEXT:    addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_shlx_i64:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    shlxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; HASWELL-NEXT:    shlxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; HASWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_shlx_i64:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    shlxq %rsi, %rdi, %rcx # sched: [1:1.00]
+; SKYLAKE-NEXT:    shlxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_shlx_i64:
+; KNL:       # BB#0:
+; KNL-NEXT:    shlxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; KNL-NEXT:    shlxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; KNL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_shlx_i64:
 ; ZNVER1:       # BB#0:
@@ -406,12 +490,26 @@ define i32 @test_shrx_i32(i32 %a0, i32 %
 ; GENERIC-NEXT:    addl %ecx, %eax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_shrx_i32:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    shrxl %esi, %edi, %ecx # sched: [1:0.50]
-; COMMON-NEXT:    shrxl %esi, (%rdx), %eax # sched: [1:0.50]
-; COMMON-NEXT:    addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_shrx_i32:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    shrxl %esi, %edi, %ecx # sched: [1:0.50]
+; HASWELL-NEXT:    shrxl %esi, (%rdx), %eax # sched: [1:0.50]
+; HASWELL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_shrx_i32:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    shrxl %esi, %edi, %ecx # sched: [1:1.00]
+; SKYLAKE-NEXT:    shrxl %esi, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_shrx_i32:
+; KNL:       # BB#0:
+; KNL-NEXT:    shrxl %esi, %edi, %ecx # sched: [1:0.50]
+; KNL-NEXT:    shrxl %esi, (%rdx), %eax # sched: [1:0.50]
+; KNL-NEXT:    addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_shrx_i32:
 ; ZNVER1:       # BB#0:
@@ -434,12 +532,26 @@ define i64 @test_shrx_i64(i64 %a0, i64 %
 ; GENERIC-NEXT:    addq %rcx, %rax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
-; COMMON-LABEL: test_shrx_i64:
-; COMMON:       # BB#0:
-; COMMON-NEXT:    shrxq %rsi, %rdi, %rcx # sched: [1:0.50]
-; COMMON-NEXT:    shrxq %rsi, (%rdx), %rax # sched: [1:0.50]
-; COMMON-NEXT:    addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT:    retq # sched: [2:1.00]
+; HASWELL-LABEL: test_shrx_i64:
+; HASWELL:       # BB#0:
+; HASWELL-NEXT:    shrxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; HASWELL-NEXT:    shrxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; HASWELL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT:    retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_shrx_i64:
+; SKYLAKE:       # BB#0:
+; SKYLAKE-NEXT:    shrxq %rsi, %rdi, %rcx # sched: [1:1.00]
+; SKYLAKE-NEXT:    shrxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT:    retq # sched: [2:1.00]
+;
+; KNL-LABEL: test_shrx_i64:
+; KNL:       # BB#0:
+; KNL-NEXT:    shrxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; KNL-NEXT:    shrxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; KNL-NEXT:    addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT:    retq # sched: [2:1.00]
 ;
 ; ZNVER1-LABEL: test_shrx_i64:
 ; ZNVER1:       # BB#0:

Modified: llvm/trunk/test/CodeGen/X86/f16c-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/f16c-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/f16c-schedule.ll Mon Sep 18 23:19:27 2017
@@ -30,9 +30,9 @@ define <4 x float> @test_vcvtph2ps_128(<
 ;
 ; SKYLAKE-LABEL: test_vcvtph2ps_128:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtph2ps_128:
@@ -80,9 +80,9 @@ define <8 x float> @test_vcvtph2ps_256(<
 ;
 ; SKYLAKE-LABEL: test_vcvtph2ps_256:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtph2ps_256:
@@ -127,8 +127,8 @@ define <8 x i16> @test_vcvtps2ph_128(<4
 ;
 ; SKYLAKE-LABEL: test_vcvtps2ph_128:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [5:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtps2ph_128:
@@ -174,8 +174,8 @@ define <8 x i16> @test_vcvtps2ph_256(<8
 ;
 ; SKYLAKE-LABEL: test_vcvtps2ph_256:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:1.00]
-; SKYLAKE-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;

Modified: llvm/trunk/test/CodeGen/X86/fma-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fma-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fma-schedule.ll Mon Sep 18 23:19:27 2017
@@ -28,8 +28,8 @@ define <2 x double> @test_vfmadd213pd(<2
 ;
 ; SKYLAKE-LABEL: test_vfmadd213pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmadd213pd:
@@ -64,8 +64,8 @@ define <4 x double> @test_vfmadd213pd_ym
 ;
 ; SKYLAKE-LABEL: test_vfmadd213pd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmadd213pd_ymm:
@@ -100,8 +100,8 @@ define <4 x float> @test_vfmadd213ps(<4
 ;
 ; SKYLAKE-LABEL: test_vfmadd213ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmadd213ps:
@@ -136,8 +136,8 @@ define <8 x float> @test_vfmadd213ps_ymm
 ;
 ; SKYLAKE-LABEL: test_vfmadd213ps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmadd213ps_ymm:
@@ -172,8 +172,8 @@ define <2 x double> @test_vfmadd213sd(<2
 ;
 ; SKYLAKE-LABEL: test_vfmadd213sd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmadd213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmadd213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmadd213sd:
@@ -208,8 +208,8 @@ define <4 x float> @test_vfmadd213ss(<4
 ;
 ; SKYLAKE-LABEL: test_vfmadd213ss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmadd213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmadd213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmadd213ss:
@@ -256,8 +256,8 @@ define <2 x double> @test_vfmaddsubpd(<2
 ;
 ; SKYLAKE-LABEL: test_vfmaddsubpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmaddsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmaddsubpd:
@@ -292,8 +292,8 @@ define <4 x double> @test_vfmaddsubpd_ym
 ;
 ; SKYLAKE-LABEL: test_vfmaddsubpd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmaddsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmaddsubpd_ymm:
@@ -328,8 +328,8 @@ define <4 x float> @test_vfmaddsubps(<4
 ;
 ; SKYLAKE-LABEL: test_vfmaddsubps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmaddsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmaddsubps:
@@ -364,8 +364,8 @@ define <8 x float> @test_vfmaddsubps_ymm
 ;
 ; SKYLAKE-LABEL: test_vfmaddsubps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmaddsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmaddsubps_ymm:
@@ -412,8 +412,8 @@ define <2 x double> @test_vfmsubaddpd(<2
 ;
 ; SKYLAKE-LABEL: test_vfmsubaddpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsubadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsubaddpd:
@@ -448,8 +448,8 @@ define <4 x double> @test_vfmsubaddpd_ym
 ;
 ; SKYLAKE-LABEL: test_vfmsubaddpd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsubadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsubaddpd_ymm:
@@ -484,8 +484,8 @@ define <4 x float> @test_vfmsubaddps(<4
 ;
 ; SKYLAKE-LABEL: test_vfmsubaddps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsubadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsubaddps:
@@ -520,8 +520,8 @@ define <8 x float> @test_vfmsubaddps_ymm
 ;
 ; SKYLAKE-LABEL: test_vfmsubaddps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsubadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsubaddps_ymm:
@@ -568,8 +568,8 @@ define <2 x double> @test_vfmsub213pd(<2
 ;
 ; SKYLAKE-LABEL: test_vfmsub213pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsub213pd:
@@ -604,8 +604,8 @@ define <4 x double> @test_vfmsub213pd_ym
 ;
 ; SKYLAKE-LABEL: test_vfmsub213pd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsub213pd_ymm:
@@ -640,8 +640,8 @@ define <4 x float> @test_vfmsub213ps(<4
 ;
 ; SKYLAKE-LABEL: test_vfmsub213ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsub213ps:
@@ -676,8 +676,8 @@ define <8 x float> @test_vfmsub213ps_ymm
 ;
 ; SKYLAKE-LABEL: test_vfmsub213ps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsub213ps_ymm:
@@ -712,8 +712,8 @@ define <2 x double> @test_vfmsub213sd(<2
 ;
 ; SKYLAKE-LABEL: test_vfmsub213sd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsub213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsub213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsub213sd:
@@ -748,8 +748,8 @@ define <4 x float> @test_vfmsub213ss(<4
 ;
 ; SKYLAKE-LABEL: test_vfmsub213ss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfmsub213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfmsub213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfmsub213ss:
@@ -796,8 +796,8 @@ define <2 x double> @test_vfnmadd213pd(<
 ;
 ; SKYLAKE-LABEL: test_vfnmadd213pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmadd213pd:
@@ -832,8 +832,8 @@ define <4 x double> @test_vfnmadd213pd_y
 ;
 ; SKYLAKE-LABEL: test_vfnmadd213pd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmadd213pd_ymm:
@@ -868,8 +868,8 @@ define <4 x float> @test_vfnmadd213ps(<4
 ;
 ; SKYLAKE-LABEL: test_vfnmadd213ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmadd213ps:
@@ -904,8 +904,8 @@ define <8 x float> @test_vfnmadd213ps_ym
 ;
 ; SKYLAKE-LABEL: test_vfnmadd213ps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmadd213ps_ymm:
@@ -940,8 +940,8 @@ define <2 x double> @test_vfnmadd213sd(<
 ;
 ; SKYLAKE-LABEL: test_vfnmadd213sd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmadd213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmadd213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmadd213sd:
@@ -976,8 +976,8 @@ define <4 x float> @test_vfnmadd213ss(<4
 ;
 ; SKYLAKE-LABEL: test_vfnmadd213ss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmadd213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmadd213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmadd213ss:
@@ -1024,8 +1024,8 @@ define <2 x double> @test_vfnmsub213pd(<
 ;
 ; SKYLAKE-LABEL: test_vfnmsub213pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmsub213pd:
@@ -1060,8 +1060,8 @@ define <4 x double> @test_vfnmsub213pd_y
 ;
 ; SKYLAKE-LABEL: test_vfnmsub213pd_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmsub213pd_ymm:
@@ -1096,8 +1096,8 @@ define <4 x float> @test_vfnmsub213ps(<4
 ;
 ; SKYLAKE-LABEL: test_vfnmsub213ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmsub213ps:
@@ -1132,8 +1132,8 @@ define <8 x float> @test_vfnmsub213ps_ym
 ;
 ; SKYLAKE-LABEL: test_vfnmsub213ps_ymm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmsub213ps_ymm:
@@ -1168,8 +1168,8 @@ define <2 x double> @test_vfnmsub213sd(<
 ;
 ; SKYLAKE-LABEL: test_vfnmsub213sd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmsub213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmsub213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmsub213sd:
@@ -1204,8 +1204,8 @@ define <4 x float> @test_vfnmsub213ss(<4
 ;
 ; SKYLAKE-LABEL: test_vfnmsub213ss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vfnmsub213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vfnmsub213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; KNL-LABEL: test_vfnmsub213ss:

Modified: llvm/trunk/test/CodeGen/X86/recip-fastmath.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/recip-fastmath.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/recip-fastmath.ll (original)
+++ llvm/trunk/test/CodeGen/X86/recip-fastmath.ll Mon Sep 18 23:19:27 2017
@@ -61,11 +61,17 @@ define float @f32_no_estimate(float %x)
 ; HASWELL-NO-FMA-NEXT:    vdivss %xmm0, %xmm1, %xmm0
 ; HASWELL-NO-FMA-NEXT:    retq
 ;
-; AVX512-LABEL: f32_no_estimate:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
-; AVX512-NEXT:    vdivss %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_no_estimate:
+; KNL:       # BB#0:
+; KNL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
+; KNL-NEXT:    vdivss %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_no_estimate:
+; SKX:       # BB#0:
+; SKX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKX-NEXT:    vdivss %xmm0, %xmm1, %xmm0 # sched: [11:1.00]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 1.0, %x
   ret float %div
 }
@@ -136,12 +142,19 @@ define float @f32_one_step(float %x) #1
 ; HASWELL-NO-FMA-NEXT:    vaddss %xmm0, %xmm1, %xmm0
 ; HASWELL-NO-FMA-NEXT:    retq
 ;
-; AVX512-LABEL: f32_one_step:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_one_step:
+; KNL:       # BB#0:
+; KNL-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; KNL-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_one_step:
+; SKX:       # BB#0:
+; SKX-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; SKX-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 1.0, %x
   ret float %div
 }
@@ -242,16 +255,27 @@ define float @f32_two_step(float %x) #2
 ; HASWELL-NO-FMA-NEXT:    vaddss %xmm0, %xmm1, %xmm0
 ; HASWELL-NO-FMA-NEXT:    retq
 ;
-; AVX512-LABEL: f32_two_step:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
-; AVX512-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
-; AVX512-NEXT:    vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [5:0.50]
-; AVX512-NEXT:    vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm3, %xmm3, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_two_step:
+; KNL:       # BB#0:
+; KNL-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; KNL-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
+; KNL-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
+; KNL-NEXT:    vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [5:0.50]
+; KNL-NEXT:    vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm3, %xmm3, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_two_step:
+; SKX:       # BB#0:
+; SKX-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; SKX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKX-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
+; SKX-NEXT:    vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm3, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 1.0, %x
   ret float %div
 }
@@ -300,11 +324,17 @@ define <4 x float> @v4f32_no_estimate(<4
 ; HASWELL-NO-FMA-NEXT:    vdivps %xmm0, %xmm1, %xmm0
 ; HASWELL-NO-FMA-NEXT:    retq
 ;
-; AVX512-LABEL: v4f32_no_estimate:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] sched: [1:0.50]
-; AVX512-NEXT:    vdivps %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: v4f32_no_estimate:
+; KNL:       # BB#0:
+; KNL-NEXT:    vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] sched: [1:0.50]
+; KNL-NEXT:    vdivps %xmm0, %xmm1, %xmm0 # sched: [13:1.00]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: v4f32_no_estimate:
+; SKX:       # BB#0:
+; SKX-NEXT:    vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] sched: [1:0.50]
+; SKX-NEXT:    vdivps %xmm0, %xmm1, %xmm0 # sched: [11:1.00]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
   ret <4 x float> %div
 }
@@ -388,7 +418,7 @@ define <4 x float> @v4f32_one_step(<4 x
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %xmm0, %xmm1
 ; SKX-NEXT:    vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0
-; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
   ret <4 x float> %div
@@ -506,10 +536,10 @@ define <4 x float> @v4f32_two_step(<4 x
 ; SKX-NEXT:    vrcp14ps %xmm0, %xmm1
 ; SKX-NEXT:    vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [1:0.50]
 ; SKX-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
-; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm3 # sched: [5:0.50]
-; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm3, %xmm0 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %xmm3, %xmm3, %xmm0 # sched: [5:0.50]
+; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm3, %xmm3, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x
   ret <4 x float> %div
@@ -562,11 +592,17 @@ define <8 x float> @v8f32_no_estimate(<8
 ; HASWELL-NO-FMA-NEXT:    vdivps %ymm0, %ymm1, %ymm0
 ; HASWELL-NO-FMA-NEXT:    retq
 ;
-; AVX512-LABEL: v8f32_no_estimate:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vbroadcastss {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1] sched: [1:0.50]
-; AVX512-NEXT:    vdivps %ymm0, %ymm1, %ymm0 # sched: [21:2.00]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: v8f32_no_estimate:
+; KNL:       # BB#0:
+; KNL-NEXT:    vbroadcastss {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1] sched: [1:0.50]
+; KNL-NEXT:    vdivps %ymm0, %ymm1, %ymm0 # sched: [21:2.00]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: v8f32_no_estimate:
+; SKX:       # BB#0:
+; SKX-NEXT:    vbroadcastss {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1] sched: [1:0.50]
+; SKX-NEXT:    vdivps %ymm0, %ymm1, %ymm0 # sched: [11:1.00]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
   ret <8 x float> %div
 }
@@ -657,7 +693,7 @@ define <8 x float> @v8f32_one_step(<8 x
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %ymm0, %ymm1
 ; SKX-NEXT:    vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0
-; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [5:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
   ret <8 x float> %div
@@ -788,10 +824,10 @@ define <8 x float> @v8f32_two_step(<8 x
 ; SKX-NEXT:    vrcp14ps %ymm0, %ymm1
 ; SKX-NEXT:    vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [1:0.50]
 ; SKX-NEXT:    vmovaps %ymm1, %ymm3 # sched: [1:1.00]
-; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm3 # sched: [5:0.50]
-; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm3, %ymm0 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %ymm3, %ymm3, %ymm0 # sched: [5:0.50]
+; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm3 # sched: [4:0.50]
+; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm3, %ymm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm3, %ymm3, %ymm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
   ret <8 x float> %div

Modified: llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/recip-fastmath2.ll Mon Sep 18 23:19:27 2017
@@ -54,11 +54,17 @@ define float @f32_no_step_2(float %x) #3
 ; HASWELL-NO-FMA-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
 ; HASWELL-NO-FMA-NEXT:    retq # sched: [2:1.00]
 ;
-; AVX512-LABEL: f32_no_step_2:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm0
-; AVX512-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_no_step_2:
+; KNL:       # BB#0:
+; KNL-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm0
+; KNL-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_no_step_2:
+; SKX:       # BB#0:
+; SKX-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm0
+; SKX-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 1234.0, %x
   ret float %div
 }
@@ -136,13 +142,21 @@ define float @f32_one_step_2(float %x) #
 ; HASWELL-NO-FMA-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
 ; HASWELL-NO-FMA-NEXT:    retq # sched: [2:1.00]
 ;
-; AVX512-LABEL: f32_one_step_2:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_one_step_2:
+; KNL:       # BB#0:
+; KNL-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; KNL-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_one_step_2:
+; SKX:       # BB#0:
+; SKX-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; SKX-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 3456.0, %x
   ret float %div
 }
@@ -227,14 +241,23 @@ define float @f32_one_step_2_divs(float
 ; HASWELL-NO-FMA-NEXT:    vmulss %xmm0, %xmm1, %xmm0 # sched: [5:0.50]
 ; HASWELL-NO-FMA-NEXT:    retq # sched: [2:1.00]
 ;
-; AVX512-LABEL: f32_one_step_2_divs:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm1 # sched: [5:0.50]
-; AVX512-NEXT:    vmulss %xmm0, %xmm1, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_one_step_2_divs:
+; KNL:       # BB#0:
+; KNL-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; KNL-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm1 # sched: [5:0.50]
+; KNL-NEXT:    vmulss %xmm0, %xmm1, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_one_step_2_divs:
+; SKX:       # BB#0:
+; SKX-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; SKX-NEXT:    vfnmadd213ss {{.*}}(%rip), %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm1 # sched: [4:0.50]
+; SKX-NEXT:    vmulss %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 3456.0, %x
   %div2 = fdiv fast float %div, %x
   ret float %div2
@@ -343,17 +366,29 @@ define float @f32_two_step_2(float %x) #
 ; HASWELL-NO-FMA-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
 ; HASWELL-NO-FMA-NEXT:    retq # sched: [2:1.00]
 ;
-; AVX512-LABEL: f32_two_step_2:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
-; AVX512-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
-; AVX512-NEXT:    vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [5:0.50]
-; AVX512-NEXT:    vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vfmadd132ss %xmm3, %xmm3, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
-; AVX512-NEXT:    retq # sched: [2:1.00]
+; KNL-LABEL: f32_two_step_2:
+; KNL:       # BB#0:
+; KNL-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; KNL-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
+; KNL-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
+; KNL-NEXT:    vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [5:0.50]
+; KNL-NEXT:    vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vfmadd132ss %xmm3, %xmm3, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
+; KNL-NEXT:    retq # sched: [2:1.00]
+;
+; SKX-LABEL: f32_two_step_2:
+; SKX:       # BB#0:
+; SKX-NEXT:    vrcp14ss %xmm0, %xmm0, %xmm1
+; SKX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKX-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
+; SKX-NEXT:    vfnmadd213ss %xmm2, %xmm0, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm1, %xmm1, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfnmadd213ss %xmm2, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ss %xmm3, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast float 6789.0, %x
   ret float %div
 }
@@ -445,8 +480,8 @@ define <4 x float> @v4f32_one_step2(<4 x
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %xmm0, %xmm1
 ; SKX-NEXT:    vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0
-; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
-; SKX-NEXT:    vmulps {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %x
   ret <4 x float> %div
@@ -547,9 +582,9 @@ define <4 x float> @v4f32_one_step_2_div
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %xmm0, %xmm1
 ; SKX-NEXT:    vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0
-; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [5:0.50]
-; SKX-NEXT:    vmulps {{.*}}(%rip), %xmm0, %xmm1 # sched: [5:0.50]
-; SKX-NEXT:    vmulps %xmm0, %xmm1, %xmm0 # sched: [5:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %xmm0, %xmm1 # sched: [4:0.50]
+; SKX-NEXT:    vmulps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %x
   %div2 = fdiv fast <4 x float> %div, %x
@@ -676,11 +711,11 @@ define <4 x float> @v4f32_two_step2(<4 x
 ; SKX-NEXT:    vrcp14ps %xmm0, %xmm1
 ; SKX-NEXT:    vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [1:0.50]
 ; SKX-NEXT:    vmovaps %xmm1, %xmm3 # sched: [1:1.00]
-; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm3 # sched: [5:0.50]
-; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm3, %xmm0 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %xmm3, %xmm3, %xmm0 # sched: [5:0.50]
-; SKX-NEXT:    vmulps {{.*}}(%rip), %xmm0, %xmm0 # sched: [5:0.50]
+; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm1, %xmm1, %xmm3 # sched: [4:0.50]
+; SKX-NEXT:    vfnmadd213ps %xmm2, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %xmm3, %xmm3, %xmm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %x
   ret <4 x float> %div
@@ -781,8 +816,8 @@ define <8 x float> @v8f32_one_step2(<8 x
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %ymm0, %ymm1
 ; SKX-NEXT:    vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0
-; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [5:0.50]
-; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [5:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
   ret <8 x float> %div
@@ -892,9 +927,9 @@ define <8 x float> @v8f32_one_step_2_div
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %ymm0, %ymm1
 ; SKX-NEXT:    vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0
-; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [5:0.50]
-; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm1 # sched: [5:0.50]
-; SKX-NEXT:    vmulps %ymm0, %ymm1, %ymm0 # sched: [5:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm1 # sched: [4:0.50]
+; SKX-NEXT:    vmulps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
   %div2 = fdiv fast <8 x float> %div, %x
@@ -1035,11 +1070,11 @@ define <8 x float> @v8f32_two_step2(<8 x
 ; SKX-NEXT:    vrcp14ps %ymm0, %ymm1
 ; SKX-NEXT:    vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [1:0.50]
 ; SKX-NEXT:    vmovaps %ymm1, %ymm3 # sched: [1:1.00]
-; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm3 # sched: [5:0.50]
-; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm3, %ymm0 # sched: [5:0.50]
-; SKX-NEXT:    vfmadd132ps %ymm3, %ymm3, %ymm0 # sched: [5:0.50]
-; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [5:0.50]
+; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm1, %ymm1, %ymm3 # sched: [4:0.50]
+; SKX-NEXT:    vfnmadd213ps %ymm2, %ymm3, %ymm0 # sched: [4:0.50]
+; SKX-NEXT:    vfmadd132ps %ymm3, %ymm3, %ymm0 # sched: [4:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
   ret <8 x float> %div
@@ -1149,7 +1184,7 @@ define <8 x float> @v8f32_no_step2(<8 x
 ; SKX-LABEL: v8f32_no_step2:
 ; SKX:       # BB#0:
 ; SKX-NEXT:    vrcp14ps %ymm0, %ymm0
-; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [5:0.50]
+; SKX-NEXT:    vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [2:1.00]
   %div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
   ret <8 x float> %div

Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Mon Sep 18 23:19:27 2017
@@ -42,8 +42,8 @@ define <4 x float> @test_addps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_addps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addps:
@@ -96,8 +96,8 @@ define float @test_addss(float %a0, floa
 ;
 ; SKYLAKE-LABEL: test_addss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addss:
@@ -154,8 +154,8 @@ define <4 x float> @test_andps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_andps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vandps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andps:
@@ -216,8 +216,8 @@ define <4 x float> @test_andnotps(<4 x f
 ;
 ; SKYLAKE-LABEL: test_andnotps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandnps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandnps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vandnps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandnps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andnotps:
@@ -281,9 +281,9 @@ define <4 x float> @test_cmpps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_cmpps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vorps %xmm0, %xmm1, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vorps %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cmpps:
@@ -342,7 +342,7 @@ define float @test_cmpss(float %a0, floa
 ; SKYLAKE-LABEL: test_cmpss:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cmpss:
@@ -441,12 +441,12 @@ define i32 @test_comiss(<4 x float> %a0,
 ; SKYLAKE-LABEL: test_comiss:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcomiss %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %cl # sched: [1:0.50]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %cl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT:    vcomiss (%rdi), %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %dl # sched: [1:0.50]
+; SKYLAKE-NEXT:    vcomiss (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %dl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    orb %cl, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    movzbl %dl, %eax # sched: [1:0.25]
@@ -525,9 +525,9 @@ define float @test_cvtsi2ss(i32 %a0, i32
 ;
 ; SKYLAKE-LABEL: test_cvtsi2ss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
-; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
+; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2ss:
@@ -588,9 +588,9 @@ define float @test_cvtsi2ssq(i64 %a0, i6
 ;
 ; SKYLAKE-LABEL: test_cvtsi2ssq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
-; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
+; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2ssq:
@@ -651,8 +651,8 @@ define i32 @test_cvtss2si(float %a0, flo
 ;
 ; SKYLAKE-LABEL: test_cvtss2si:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtss2si %xmm0, %ecx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtss2si (%rdi), %eax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvtss2si %xmm0, %ecx # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvtss2si (%rdi), %eax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -717,8 +717,8 @@ define i64 @test_cvtss2siq(float %a0, fl
 ;
 ; SKYLAKE-LABEL: test_cvtss2siq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtss2si %xmm0, %rcx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtss2si (%rdi), %rax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvtss2si %xmm0, %rcx # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvtss2si (%rdi), %rax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -783,8 +783,8 @@ define i32 @test_cvttss2si(float %a0, fl
 ;
 ; SKYLAKE-LABEL: test_cvttss2si:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttss2si %xmm0, %ecx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvttss2si (%rdi), %eax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvttss2si %xmm0, %ecx # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvttss2si (%rdi), %eax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -846,8 +846,8 @@ define i64 @test_cvttss2siq(float %a0, f
 ;
 ; SKYLAKE-LABEL: test_cvttss2siq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttss2si %xmm0, %rcx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvttss2si (%rdi), %rax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvttss2si %xmm0, %rcx # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvttss2si (%rdi), %rax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -904,8 +904,8 @@ define <4 x float> @test_divps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_divps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdivps %xmm1, %xmm0, %xmm0 # sched: [13:1.00]
-; SKYLAKE-NEXT:    vdivps (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
+; SKYLAKE-NEXT:    vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
+; SKYLAKE-NEXT:    vdivps (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_divps:
@@ -958,8 +958,8 @@ define float @test_divss(float %a0, floa
 ;
 ; SKYLAKE-LABEL: test_divss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdivss %xmm1, %xmm0, %xmm0 # sched: [13:1.00]
-; SKYLAKE-NEXT:    vdivss (%rdi), %xmm0, %xmm0 # sched: [13:1.00]
+; SKYLAKE-NEXT:    vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
+; SKYLAKE-NEXT:    vdivss (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_divss:
@@ -1068,8 +1068,8 @@ define <4 x float> @test_maxps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_maxps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaxps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vmaxps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmaxps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vmaxps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_maxps:
@@ -1123,8 +1123,8 @@ define <4 x float> @test_maxss(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_maxss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaxss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vmaxss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmaxss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vmaxss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_maxss:
@@ -1178,8 +1178,8 @@ define <4 x float> @test_minps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_minps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vminps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vminps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vminps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vminps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_minps:
@@ -1233,8 +1233,8 @@ define <4 x float> @test_minss(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_minss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vminss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vminss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vminss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vminss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_minss:
@@ -1294,7 +1294,7 @@ define void @test_movaps(<4 x float> *%a
 ; SKYLAKE-LABEL: test_movaps:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovaps (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovaps %xmm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1412,7 +1412,7 @@ define void @test_movhps(<4 x float> %a0
 ; SKYLAKE-LABEL: test_movhps:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1475,7 +1475,7 @@ define <4 x float> @test_movlhps(<4 x fl
 ; SKYLAKE-LABEL: test_movlhps:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movlhps:
@@ -1533,7 +1533,7 @@ define void @test_movlps(<4 x float> %a0
 ; SKYLAKE-LABEL: test_movlps:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovlps %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1590,7 +1590,7 @@ define i32 @test_movmskps(<4 x float> %a
 ;
 ; SKYLAKE-LABEL: test_movmskps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmovmskps %xmm0, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmovmskps %xmm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movmskps:
@@ -1696,7 +1696,7 @@ define void @test_movss_mem(float* %a0,
 ; SKYLAKE-LABEL: test_movss_mem:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddss %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddss %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovss %xmm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1753,7 +1753,7 @@ define <4 x float> @test_movss_reg(<4 x
 ;
 ; SKYLAKE-LABEL: test_movss_reg:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]
+; SKYLAKE-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movss_reg:
@@ -1808,7 +1808,7 @@ define void @test_movups(<4 x float> *%a
 ; SKYLAKE-LABEL: test_movups:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovups (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovups %xmm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1864,8 +1864,8 @@ define <4 x float> @test_mulps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_mulps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmulps %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vmulps (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vmulps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vmulps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mulps:
@@ -1918,8 +1918,8 @@ define float @test_mulss(float %a0, floa
 ;
 ; SKYLAKE-LABEL: test_mulss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmulss %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vmulss (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vmulss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vmulss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mulss:
@@ -1976,8 +1976,8 @@ define <4 x float> @test_orps(<4 x float
 ;
 ; SKYLAKE-LABEL: test_orps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vorps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vorps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vorps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vorps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_orps:
@@ -2092,9 +2092,9 @@ define <4 x float> @test_rcpps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_rcpps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vrcpps %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vrcpps (%rdi), %xmm1 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vrcpps %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vrcpps (%rdi), %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_rcpps:
@@ -2163,10 +2163,10 @@ define <4 x float> @test_rcpss(float %a0
 ;
 ; SKYLAKE-LABEL: test_rcpss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vrcpss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vrcpss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
 ; SKYLAKE-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
-; SKYLAKE-NEXT:    vrcpss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vrcpss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_rcpss:
@@ -2234,9 +2234,9 @@ define <4 x float> @test_rsqrtps(<4 x fl
 ;
 ; SKYLAKE-LABEL: test_rsqrtps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vrsqrtps %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vrsqrtps (%rdi), %xmm1 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vrsqrtps %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vrsqrtps (%rdi), %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_rsqrtps:
@@ -2305,10 +2305,10 @@ define <4 x float> @test_rsqrtss(float %
 ;
 ; SKYLAKE-LABEL: test_rsqrtss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
 ; SKYLAKE-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
-; SKYLAKE-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_rsqrtss:
@@ -2484,9 +2484,9 @@ define <4 x float> @test_sqrtps(<4 x flo
 ;
 ; SKYLAKE-LABEL: test_sqrtps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsqrtps %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT:    vsqrtps (%rdi), %xmm1 # sched: [14:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsqrtps %xmm0, %xmm0 # sched: [12:1.00]
+; SKYLAKE-NEXT:    vsqrtps (%rdi), %xmm1 # sched: [12:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_sqrtps:
@@ -2555,10 +2555,10 @@ define <4 x float> @test_sqrtss(<4 x flo
 ;
 ; SKYLAKE-LABEL: test_sqrtss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0 # sched: [14:1.00]
+; SKYLAKE-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]
 ; SKYLAKE-NEXT:    vmovaps (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vsqrtss %xmm1, %xmm1, %xmm1 # sched: [14:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_sqrtss:
@@ -2673,8 +2673,8 @@ define <4 x float> @test_subps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_subps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vsubps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vsubps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_subps:
@@ -2727,8 +2727,8 @@ define float @test_subss(float %a0, floa
 ;
 ; SKYLAKE-LABEL: test_subss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsubss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vsubss (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsubss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vsubss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_subss:
@@ -2822,12 +2822,12 @@ define i32 @test_ucomiss(<4 x float> %a0
 ; SKYLAKE-LABEL: test_ucomiss:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vucomiss %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %cl # sched: [1:0.50]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %cl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT:    vucomiss (%rdi), %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %dl # sched: [1:0.50]
+; SKYLAKE-NEXT:    vucomiss (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %dl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    orb %cl, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    movzbl %dl, %eax # sched: [1:0.25]
@@ -3021,8 +3021,8 @@ define <4 x float> @test_xorps(<4 x floa
 ;
 ; SKYLAKE-LABEL: test_xorps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vxorps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vxorps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_xorps:

Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Mon Sep 18 23:19:27 2017
@@ -42,8 +42,8 @@ define <2 x double> @test_addpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_addpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addpd:
@@ -96,8 +96,8 @@ define double @test_addsd(double %a0, do
 ;
 ; SKYLAKE-LABEL: test_addsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addsd:
@@ -155,9 +155,9 @@ define <2 x double> @test_andpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_andpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andpd:
@@ -222,9 +222,9 @@ define <2 x double> @test_andnotpd(<2 x
 ;
 ; SKYLAKE-LABEL: test_andnotpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vandnpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vandnpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_andnotpd:
@@ -291,9 +291,9 @@ define <2 x double> @test_cmppd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_cmppd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vorpd %xmm0, %xmm1, %xmm0 # sched: [1:1.00]
+; SKYLAKE-NEXT:    vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cmppd:
@@ -352,7 +352,7 @@ define double @test_cmpsd(double %a0, do
 ; SKYLAKE-LABEL: test_cmpsd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cmpsd:
@@ -451,12 +451,12 @@ define i32 @test_comisd(<2 x double> %a0
 ; SKYLAKE-LABEL: test_comisd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcomisd %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %cl # sched: [1:0.50]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %cl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT:    vcomisd (%rdi), %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %dl # sched: [1:0.50]
+; SKYLAKE-NEXT:    vcomisd (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %dl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    orb %cl, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    movzbl %dl, %eax # sched: [1:0.25]
@@ -535,9 +535,9 @@ define <2 x double> @test_cvtdq2pd(<4 x
 ;
 ; SKYLAKE-LABEL: test_cvtdq2pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtdq2pd %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtdq2pd (%rdi), %xmm1 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtdq2pd %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtdq2pd (%rdi), %xmm1 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtdq2pd:
@@ -601,9 +601,9 @@ define <4 x float> @test_cvtdq2ps(<4 x i
 ;
 ; SKYLAKE-LABEL: test_cvtdq2ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtdq2ps %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcvtdq2ps (%rdi), %xmm1 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtdq2ps %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcvtdq2ps (%rdi), %xmm1 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtdq2ps:
@@ -665,8 +665,8 @@ define <4 x i32> @test_cvtpd2dq(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_cvtpd2dq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtpd2dq %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtpd2dqx (%rdi), %xmm1 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvtpd2dq %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
 ; SKYLAKE-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -730,9 +730,9 @@ define <4 x float> @test_cvtpd2ps(<2 x d
 ;
 ; SKYLAKE-LABEL: test_cvtpd2ps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtpd2ps %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtpd2psx (%rdi), %xmm1 # sched: [7:1.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtpd2ps %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtpd2ps:
@@ -795,8 +795,8 @@ define <4 x i32> @test_cvtps2dq(<4 x flo
 ;
 ; SKYLAKE-LABEL: test_cvtps2dq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtps2dq %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcvtps2dq (%rdi), %xmm1 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtps2dq %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcvtps2dq (%rdi), %xmm1 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -860,9 +860,9 @@ define <2 x double> @test_cvtps2pd(<4 x
 ;
 ; SKYLAKE-LABEL: test_cvtps2pd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtps2pd %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vcvtps2pd (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtps2pd %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtps2pd (%rdi), %xmm1 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtps2pd:
@@ -925,8 +925,8 @@ define i32 @test_cvtsd2si(double %a0, do
 ;
 ; SKYLAKE-LABEL: test_cvtsd2si:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsd2si %xmm0, %ecx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtsd2si (%rdi), %eax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvtsd2si %xmm0, %ecx # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvtsd2si (%rdi), %eax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -991,8 +991,8 @@ define i64 @test_cvtsd2siq(double %a0, d
 ;
 ; SKYLAKE-LABEL: test_cvtsd2siq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsd2si %xmm0, %rcx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtsd2si (%rdi), %rax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvtsd2si %xmm0, %rcx # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvtsd2si (%rdi), %rax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1063,10 +1063,10 @@ define float @test_cvtsd2ss(double %a0,
 ;
 ; SKYLAKE-LABEL: test_cvtsd2ss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]
 ; SKYLAKE-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]
-; SKYLAKE-NEXT:    vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsd2ss:
@@ -1129,9 +1129,9 @@ define double @test_cvtsi2sd(i32 %a0, i3
 ;
 ; SKYLAKE-LABEL: test_cvtsi2sd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
-; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
+; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2sd:
@@ -1192,9 +1192,9 @@ define double @test_cvtsi2sdq(i64 %a0, i
 ;
 ; SKYLAKE-LABEL: test_cvtsi2sdq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
-; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
+; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2sdq:
@@ -1263,10 +1263,10 @@ define double @test_cvtss2sd(float %a0,
 ;
 ; SKYLAKE-LABEL: test_cvtss2sd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [5:1.00]
 ; SKYLAKE-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
-; SKYLAKE-NEXT:    vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_cvtss2sd:
@@ -1330,8 +1330,8 @@ define <4 x i32> @test_cvttpd2dq(<2 x do
 ;
 ; SKYLAKE-LABEL: test_cvttpd2dq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttpd2dq %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvttpd2dqx (%rdi), %xmm1 # sched: [7:1.00]
+; SKYLAKE-NEXT:    vcvttpd2dq %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
 ; SKYLAKE-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1396,8 +1396,8 @@ define <4 x i32> @test_cvttps2dq(<4 x fl
 ;
 ; SKYLAKE-LABEL: test_cvttps2dq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vcvttps2dq (%rdi), %xmm1 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vcvttps2dq %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vcvttps2dq (%rdi), %xmm1 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1459,8 +1459,8 @@ define i32 @test_cvttsd2si(double %a0, d
 ;
 ; SKYLAKE-LABEL: test_cvttsd2si:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttsd2si %xmm0, %ecx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvttsd2si (%rdi), %eax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvttsd2si %xmm0, %ecx # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvttsd2si (%rdi), %eax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addl %ecx, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1522,8 +1522,8 @@ define i64 @test_cvttsd2siq(double %a0,
 ;
 ; SKYLAKE-LABEL: test_cvttsd2siq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vcvttsd2si %xmm0, %rcx # sched: [4:1.00]
-; SKYLAKE-NEXT:    vcvttsd2si (%rdi), %rax # sched: [4:1.00]
+; SKYLAKE-NEXT:    vcvttsd2si %xmm0, %rcx # sched: [6:1.00]
+; SKYLAKE-NEXT:    vcvttsd2si (%rdi), %rax # sched: [6:1.00]
 ; SKYLAKE-NEXT:    addq %rcx, %rax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1580,8 +1580,8 @@ define <2 x double> @test_divpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_divpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdivpd %xmm1, %xmm0, %xmm0 # sched: [20:1.00]
-; SKYLAKE-NEXT:    vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SKYLAKE-NEXT:    vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
+; SKYLAKE-NEXT:    vdivpd (%rdi), %xmm0, %xmm0 # sched: [14:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_divpd:
@@ -1634,8 +1634,8 @@ define double @test_divsd(double %a0, do
 ;
 ; SKYLAKE-LABEL: test_divsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdivsd %xmm1, %xmm0, %xmm0 # sched: [20:1.00]
-; SKYLAKE-NEXT:    vdivsd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SKYLAKE-NEXT:    vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
+; SKYLAKE-NEXT:    vdivsd (%rdi), %xmm0, %xmm0 # sched: [14:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_divsd:
@@ -1839,8 +1839,8 @@ define <2 x double> @test_maxpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_maxpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vmaxpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vmaxpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_maxpd:
@@ -1894,8 +1894,8 @@ define <2 x double> @test_maxsd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_maxsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vmaxsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vmaxsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_maxsd:
@@ -1949,8 +1949,8 @@ define <2 x double> @test_minpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_minpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vminpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vminpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vminpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vminpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_minpd:
@@ -2004,8 +2004,8 @@ define <2 x double> @test_minsd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_minsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vminsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vminsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vminsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vminsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_minsd:
@@ -2065,7 +2065,7 @@ define void @test_movapd(<2 x double> *%
 ; SKYLAKE-LABEL: test_movapd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovapd (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovapd %xmm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2269,7 +2269,7 @@ define i32 @test_movd(<4 x i32> %a0, i32
 ; SKYLAKE-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vmovd %xmm0, %eax # sched: [1:1.00]
+; SKYLAKE-NEXT:    vmovd %xmm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    vmovd %xmm1, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2360,7 +2360,7 @@ define i64 @test_movd_64(<2 x i64> %a0,
 ; SKYLAKE-NEXT:    vmovq {{.*#+}} xmm2 = mem[0],zero sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vmovq %xmm0, %rax # sched: [1:1.00]
+; SKYLAKE-NEXT:    vmovq %xmm0, %rax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    vmovq %xmm1, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2433,7 +2433,7 @@ define void @test_movhpd(<2 x double> %a
 ; SKYLAKE-LABEL: test_movhpd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovhpd %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2498,7 +2498,7 @@ define void @test_movlpd(<2 x double> %a
 ; SKYLAKE-LABEL: test_movlpd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovlpd %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2554,7 +2554,7 @@ define i32 @test_movmskpd(<2 x double> %
 ;
 ; SKYLAKE-LABEL: test_movmskpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmovmskpd %xmm0, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT:    vmovmskpd %xmm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movmskpd:
@@ -2659,7 +2659,7 @@ define void @test_movntpd(<2 x double> %
 ;
 ; SKYLAKE-LABEL: test_movntpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovntpd %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2778,7 +2778,7 @@ define <2 x i64> @test_movq_reg(<2 x i64
 ;
 ; SKYLAKE-LABEL: test_movq_reg:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.33]
+; SKYLAKE-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2837,7 +2837,7 @@ define void @test_movsd_mem(double* %a0,
 ; SKYLAKE-LABEL: test_movsd_mem:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddsd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddsd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovsd %xmm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2950,7 +2950,7 @@ define void @test_movupd(<2 x double> *%
 ; SKYLAKE-LABEL: test_movupd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovupd (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vmovupd %xmm0, (%rsi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3006,8 +3006,8 @@ define <2 x double> @test_mulpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_mulpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmulpd %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vmulpd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vmulpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vmulpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mulpd:
@@ -3060,8 +3060,8 @@ define double @test_mulsd(double %a0, do
 ;
 ; SKYLAKE-LABEL: test_mulsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmulsd %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
-; SKYLAKE-NEXT:    vmulsd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
+; SKYLAKE-NEXT:    vmulsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vmulsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mulsd:
@@ -3119,9 +3119,9 @@ define <2 x double> @test_orpd(<2 x doub
 ;
 ; SKYLAKE-LABEL: test_orpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vorpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vorpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vorpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_orpd:
@@ -3535,7 +3535,7 @@ define <16 x i8> @test_paddsb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_paddsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3594,7 +3594,7 @@ define <8 x i16> @test_paddsw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_paddsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3653,7 +3653,7 @@ define <16 x i8> @test_paddusb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_paddusb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3712,7 +3712,7 @@ define <8 x i16> @test_paddusw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_paddusw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpaddusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -3830,7 +3830,7 @@ define <2 x i64> @test_pand(<2 x i64> %a
 ;
 ; SKYLAKE-LABEL: test_pand:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpand (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -3899,7 +3899,7 @@ define <2 x i64> @test_pandn(<2 x i64> %
 ;
 ; SKYLAKE-LABEL: test_pandn:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpandn (%rdi), %xmm0, %xmm1 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -3963,7 +3963,7 @@ define <16 x i8> @test_pavgb(<16 x i8> %
 ;
 ; SKYLAKE-LABEL: test_pavgb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpavgb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4031,7 +4031,7 @@ define <8 x i16> @test_pavgw(<8 x i16> %
 ;
 ; SKYLAKE-LABEL: test_pavgw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpavgw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4102,9 +4102,9 @@ define <16 x i8> @test_pcmpeqb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpeqb:
@@ -4168,9 +4168,9 @@ define <4 x i32> @test_pcmpeqd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpeqd:
@@ -4234,9 +4234,9 @@ define <8 x i16> @test_pcmpeqw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpeqw:
@@ -4301,9 +4301,9 @@ define <16 x i8> @test_pcmpgtb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpgtb:
@@ -4368,9 +4368,9 @@ define <4 x i32> @test_pcmpgtd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpgtd:
@@ -4435,9 +4435,9 @@ define <8 x i16> @test_pcmpgtw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpgtw:
@@ -4494,7 +4494,7 @@ define i16 @test_pextrw(<8 x i16> %a0) {
 ;
 ; SKYLAKE-LABEL: test_pextrw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpextrw $6, %xmm0, %eax # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpextrw $6, %xmm0, %eax # sched: [3:1.00]
 ; SKYLAKE-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4612,8 +4612,8 @@ define <4 x i32> @test_pmaddwd(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pmaddwd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmaddwd:
@@ -4672,7 +4672,7 @@ define <8 x i16> @test_pmaxsw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pmaxsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4731,7 +4731,7 @@ define <16 x i8> @test_pmaxub(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_pmaxub:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4790,7 +4790,7 @@ define <8 x i16> @test_pminsw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pminsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4849,7 +4849,7 @@ define <16 x i8> @test_pminub(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_pminub:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminub %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -4901,7 +4901,7 @@ define i32 @test_pmovmskb(<16 x i8> %a0)
 ;
 ; SKYLAKE-LABEL: test_pmovmskb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmovmskb %xmm0, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT:    vpmovmskb %xmm0, %eax # sched: [2:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmovmskb:
@@ -4951,8 +4951,8 @@ define <8 x i16> @test_pmulhuw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pmulhuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmulhuw:
@@ -5006,8 +5006,8 @@ define <8 x i16> @test_pmulhw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pmulhw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulhw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmulhw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmulhw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmulhw:
@@ -5061,8 +5061,8 @@ define <8 x i16> @test_pmullw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pmullw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmullw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmullw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmullw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmullw:
@@ -5123,8 +5123,8 @@ define <2 x i64> @test_pmuludq(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmuludq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmuludq %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmuludq (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmuludq (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmuludq:
@@ -5184,7 +5184,7 @@ define <2 x i64> @test_por(<2 x i64> %a0
 ;
 ; SKYLAKE-LABEL: test_por:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -5250,8 +5250,8 @@ define <2 x i64> @test_psadbw(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_psadbw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsadbw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpsadbw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpsadbw %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vpsadbw (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_psadbw:
@@ -5507,7 +5507,7 @@ define <4 x i32> @test_pslld(<4 x i32> %
 ; SKYLAKE-LABEL: test_pslld:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpslld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpslld (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpslld (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpslld $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5622,7 +5622,7 @@ define <2 x i64> @test_psllq(<2 x i64> %
 ; SKYLAKE-LABEL: test_psllq:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsllq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsllq (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsllq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsllq $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5687,7 +5687,7 @@ define <8 x i16> @test_psllw(<8 x i16> %
 ; SKYLAKE-LABEL: test_psllw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsllw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsllw (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsllw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsllw $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5752,7 +5752,7 @@ define <4 x i32> @test_psrad(<4 x i32> %
 ; SKYLAKE-LABEL: test_psrad:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrad %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsrad (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsrad (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrad $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5817,7 +5817,7 @@ define <8 x i16> @test_psraw(<8 x i16> %
 ; SKYLAKE-LABEL: test_psraw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsraw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsraw (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsraw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsraw $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5882,7 +5882,7 @@ define <4 x i32> @test_psrld(<4 x i32> %
 ; SKYLAKE-LABEL: test_psrld:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsrld (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsrld (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrld $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -5997,7 +5997,7 @@ define <2 x i64> @test_psrlq(<2 x i64> %
 ; SKYLAKE-LABEL: test_psrlq:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrlq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsrlq (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsrlq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrlq $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -6062,7 +6062,7 @@ define <8 x i16> @test_psrlw(<8 x i16> %
 ; SKYLAKE-LABEL: test_psrlw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpsrlw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    vpsrlw (%rdi), %xmm0, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpsrlw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpsrlw $2, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -6295,7 +6295,7 @@ define <16 x i8> @test_psubsb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_psubsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -6354,7 +6354,7 @@ define <8 x i16> @test_psubsw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_psubsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -6413,7 +6413,7 @@ define <16 x i8> @test_psubusb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_psubusb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -6472,7 +6472,7 @@ define <8 x i16> @test_psubusw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_psubusw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsubusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -7078,7 +7078,7 @@ define <2 x i64> @test_pxor(<2 x i64> %a
 ;
 ; SKYLAKE-LABEL: test_pxor:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpxor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -7143,7 +7143,7 @@ define <2 x double> @test_shufpd(<2 x do
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_shufpd:
@@ -7205,9 +7205,9 @@ define <2 x double> @test_sqrtpd(<2 x do
 ;
 ; SKYLAKE-LABEL: test_sqrtpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsqrtpd %xmm0, %xmm0 # sched: [21:1.00]
-; SKYLAKE-NEXT:    vsqrtpd (%rdi), %xmm1 # sched: [21:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsqrtpd %xmm0, %xmm0 # sched: [18:1.00]
+; SKYLAKE-NEXT:    vsqrtpd (%rdi), %xmm1 # sched: [18:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_sqrtpd:
@@ -7276,10 +7276,10 @@ define <2 x double> @test_sqrtsd(<2 x do
 ;
 ; SKYLAKE-LABEL: test_sqrtsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:1.00]
+; SKYLAKE-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:1.00]
 ; SKYLAKE-NEXT:    vmovapd (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [21:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_sqrtsd:
@@ -7338,8 +7338,8 @@ define <2 x double> @test_subpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_subpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vsubpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vsubpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_subpd:
@@ -7392,8 +7392,8 @@ define double @test_subsd(double %a0, do
 ;
 ; SKYLAKE-LABEL: test_subsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vsubsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vsubsd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vsubsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vsubsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_subsd:
@@ -7487,12 +7487,12 @@ define i32 @test_ucomisd(<2 x double> %a
 ; SKYLAKE-LABEL: test_ucomisd:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vucomisd %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %cl # sched: [1:0.50]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %cl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %cl # sched: [1:0.25]
-; SKYLAKE-NEXT:    vucomisd (%rdi), %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT:    setnp %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    sete %dl # sched: [1:0.50]
+; SKYLAKE-NEXT:    vucomisd (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT:    setnp %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    sete %dl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    orb %cl, %dl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    movzbl %dl, %eax # sched: [1:0.25]
@@ -7573,7 +7573,7 @@ define <2 x double> @test_unpckhpd(<2 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_unpckhpd:
@@ -7642,7 +7642,7 @@ define <2 x double> @test_unpcklpd(<2 x
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_unpcklpd:
@@ -7703,9 +7703,9 @@ define <2 x double> @test_xorpd(<2 x dou
 ;
 ; SKYLAKE-LABEL: test_xorpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vxorpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vxorpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_xorpd:

Modified: llvm/trunk/test/CodeGen/X86/sse3-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3-schedule.ll Mon Sep 18 23:19:27 2017
@@ -42,8 +42,8 @@ define <2 x double> @test_addsubpd(<2 x
 ;
 ; SKYLAKE-LABEL: test_addsubpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addsubpd:
@@ -97,8 +97,8 @@ define <4 x float> @test_addsubps(<4 x f
 ;
 ; SKYLAKE-LABEL: test_addsubps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT:    vaddsubps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vaddsubps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_addsubps:
@@ -152,8 +152,8 @@ define <2 x double> @test_haddpd(<2 x do
 ;
 ; SKYLAKE-LABEL: test_haddpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_haddpd:
@@ -207,8 +207,8 @@ define <4 x float> @test_haddps(<4 x flo
 ;
 ; SKYLAKE-LABEL: test_haddps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_haddps:
@@ -262,8 +262,8 @@ define <2 x double> @test_hsubpd(<2 x do
 ;
 ; SKYLAKE-LABEL: test_hsubpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_hsubpd:
@@ -317,8 +317,8 @@ define <4 x float> @test_hsubps(<4 x flo
 ;
 ; SKYLAKE-LABEL: test_hsubps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
-; SKYLAKE-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
+; SKYLAKE-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
+; SKYLAKE-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_hsubps:
@@ -488,7 +488,7 @@ define <2 x double> @test_movddup(<2 x d
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movddup:
@@ -552,7 +552,7 @@ define <4 x float> @test_movshdup(<4 x f
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movshdup:
@@ -616,7 +616,7 @@ define <4 x float> @test_movsldup(<4 x f
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
 ; SKYLAKE-NEXT:    vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [1:0.50]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_movsldup:

Modified: llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-schedule.ll Mon Sep 18 23:19:27 2017
@@ -39,8 +39,8 @@ define <2 x double> @test_blendpd(<2 x d
 ;
 ; SKYLAKE-LABEL: test_blendpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.33]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.50]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -91,7 +91,7 @@ define <4 x float> @test_blendps(<4 x fl
 ;
 ; SKYLAKE-LABEL: test_blendps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.33]
+; SKYLAKE-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.50]
 ; SKYLAKE-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -145,8 +145,8 @@ define <2 x double> @test_blendvpd(<2 x
 ;
 ; SKYLAKE-LABEL: test_blendvpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:2.00]
+; SKYLAKE-NEXT:    vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]
+; SKYLAKE-NEXT:    vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_blendvpd:
@@ -200,8 +200,8 @@ define <4 x float> @test_blendvps(<4 x f
 ;
 ; SKYLAKE-LABEL: test_blendvps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:2.00]
+; SKYLAKE-NEXT:    vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]
+; SKYLAKE-NEXT:    vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_blendvps:
@@ -298,8 +298,8 @@ define <4 x float> @test_dpps(<4 x float
 ;
 ; SKYLAKE-LABEL: test_dpps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [14:2.00]
-; SKYLAKE-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [14:2.00]
+; SKYLAKE-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [13:1.33]
+; SKYLAKE-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [13:1.33]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_dpps:
@@ -436,8 +436,8 @@ define <8 x i16> @test_mpsadbw(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_mpsadbw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [7:2.00]
-; SKYLAKE-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
+; SKYLAKE-NEXT:    vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [4:2.00]
+; SKYLAKE-NEXT:    vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [4:2.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_mpsadbw:
@@ -542,8 +542,8 @@ define <16 x i8> @test_pblendvb(<16 x i8
 ;
 ; SKYLAKE-LABEL: test_pblendvb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT:    vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:2.00]
+; SKYLAKE-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]
+; SKYLAKE-NEXT:    vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pblendvb:
@@ -592,7 +592,7 @@ define <8 x i16> @test_pblendw(<8 x i16>
 ; SKYLAKE-LABEL: test_pblendw:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] sched: [1:1.00]
-; SKYLAKE-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6],mem[7] sched: [4:1.00]
+; SKYLAKE-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6],mem[7] sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pblendw:
@@ -639,7 +639,7 @@ define <2 x i64> @test_pcmpeqq(<2 x i64>
 ;
 ; SKYLAKE-LABEL: test_pcmpeqq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -689,7 +689,7 @@ define i32 @test_pextrb(<16 x i8> %a0, i
 ;
 ; SKYLAKE-LABEL: test_pextrb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpextrb $3, %xmm0, %eax # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpextrb $3, %xmm0, %eax # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpextrb $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -738,7 +738,7 @@ define i32 @test_pextrd(<4 x i32> %a0, i
 ;
 ; SKYLAKE-LABEL: test_pextrd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpextrd $3, %xmm0, %eax # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpextrd $3, %xmm0, %eax # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -786,7 +786,7 @@ define i64 @test_pextrq(<2 x i64> %a0, <
 ;
 ; SKYLAKE-LABEL: test_pextrq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpextrq $1, %xmm0, %rax # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpextrq $1, %xmm0, %rax # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -834,7 +834,7 @@ define i32 @test_pextrw(<8 x i16> %a0, i
 ;
 ; SKYLAKE-LABEL: test_pextrw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpextrw $3, %xmm0, %eax # sched: [2:1.00]
+; SKYLAKE-NEXT:    vpextrw $3, %xmm0, %eax # sched: [3:1.00]
 ; SKYLAKE-NEXT:    vpextrw $1, %xmm0, (%rdi) # sched: [1:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -883,8 +883,8 @@ define <8 x i16> @test_phminposuw(<8 x i
 ;
 ; SKYLAKE-LABEL: test_phminposuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vphminposuw (%rdi), %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vphminposuw %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vphminposuw (%rdi), %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT:    vphminposuw %xmm0, %xmm0 # sched: [4:0.33]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_phminposuw:
@@ -1084,7 +1084,7 @@ define <16 x i8> @test_pmaxsb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_pmaxsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1133,7 +1133,7 @@ define <4 x i32> @test_pmaxsd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmaxsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1182,7 +1182,7 @@ define <4 x i32> @test_pmaxud(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmaxud:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1231,7 +1231,7 @@ define <8 x i16> @test_pmaxuw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pmaxuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1280,7 +1280,7 @@ define <16 x i8> @test_pminsb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_pminsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1329,7 +1329,7 @@ define <4 x i32> @test_pminsd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pminsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1378,7 +1378,7 @@ define <4 x i32> @test_pminud(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pminud:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminud %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -1427,7 +1427,7 @@ define <8 x i16> @test_pminuw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_pminuw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpminuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -2172,8 +2172,8 @@ define <2 x i64> @test_pmuldq(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmuldq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmuldq %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmuldq (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmuldq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmuldq (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmuldq:
@@ -2222,8 +2222,8 @@ define <4 x i32> @test_pmulld(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_pmulld:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulld %xmm1, %xmm0, %xmm0 # sched: [10:2.00]
-; SKYLAKE-NEXT:    vpmulld (%rdi), %xmm0, %xmm0 # sched: [10:2.00]
+; SKYLAKE-NEXT:    vpmulld %xmm1, %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vpmulld (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmulld:
@@ -2286,10 +2286,10 @@ define i32 @test_ptest(<2 x i64> %a0, <2
 ;
 ; SKYLAKE-LABEL: test_ptest:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vptest %xmm1, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    setb %al # sched: [1:0.50]
-; SKYLAKE-NEXT:    vptest (%rdi), %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT:    setb %cl # sched: [1:0.50]
+; SKYLAKE-NEXT:    vptest %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    setb %al # sched: [1:1.00]
+; SKYLAKE-NEXT:    vptest (%rdi), %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    setb %cl # sched: [1:1.00]
 ; SKYLAKE-NEXT:    andb %al, %cl # sched: [1:0.25]
 ; SKYLAKE-NEXT:    movzbl %cl, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -2353,9 +2353,9 @@ define <2 x double> @test_roundpd(<2 x d
 ;
 ; SKYLAKE-LABEL: test_roundpd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vroundpd $7, %xmm0, %xmm0 # sched: [5:1.25]
-; SKYLAKE-NEXT:    vroundpd $7, (%rdi), %xmm1 # sched: [6:2.00]
-; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vroundpd $7, %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vroundpd $7, (%rdi), %xmm1 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_roundpd:
@@ -2411,9 +2411,9 @@ define <4 x float> @test_roundps(<4 x fl
 ;
 ; SKYLAKE-LABEL: test_roundps:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vroundps $7, %xmm0, %xmm0 # sched: [5:1.25]
-; SKYLAKE-NEXT:    vroundps $7, (%rdi), %xmm1 # sched: [6:2.00]
-; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vroundps $7, %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vroundps $7, (%rdi), %xmm1 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_roundps:
@@ -2470,9 +2470,9 @@ define <2 x double> @test_roundsd(<2 x d
 ;
 ; SKYLAKE-LABEL: test_roundsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [5:1.25]
-; SKYLAKE-NEXT:    vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_roundsd:
@@ -2529,9 +2529,9 @@ define <4 x float> @test_roundss(<4 x fl
 ;
 ; SKYLAKE-LABEL: test_roundss:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [5:1.25]
-; SKYLAKE-NEXT:    vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_roundss:

Modified: llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse42-schedule.ll Mon Sep 18 23:19:27 2017
@@ -40,7 +40,7 @@ define i32 @crc32_32_8(i32 %a0, i8 %a1,
 ; SKYLAKE-LABEL: crc32_32_8:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    crc32b %sil, %edi # sched: [3:1.00]
-; SKYLAKE-NEXT:    crc32b (%rdx), %edi # sched: [7:1.00]
+; SKYLAKE-NEXT:    crc32b (%rdx), %edi # sched: [8:1.00]
 ; SKYLAKE-NEXT:    movl %edi, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -96,7 +96,7 @@ define i32 @crc32_32_16(i32 %a0, i16 %a1
 ; SKYLAKE-LABEL: crc32_32_16:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    crc32w %si, %edi # sched: [3:1.00]
-; SKYLAKE-NEXT:    crc32w (%rdx), %edi # sched: [7:1.00]
+; SKYLAKE-NEXT:    crc32w (%rdx), %edi # sched: [8:1.00]
 ; SKYLAKE-NEXT:    movl %edi, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -152,7 +152,7 @@ define i32 @crc32_32_32(i32 %a0, i32 %a1
 ; SKYLAKE-LABEL: crc32_32_32:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    crc32l %esi, %edi # sched: [3:1.00]
-; SKYLAKE-NEXT:    crc32l (%rdx), %edi # sched: [7:1.00]
+; SKYLAKE-NEXT:    crc32l (%rdx), %edi # sched: [8:1.00]
 ; SKYLAKE-NEXT:    movl %edi, %eax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -208,7 +208,7 @@ define i64 @crc32_64_8(i64 %a0, i8 %a1,
 ; SKYLAKE-LABEL: crc32_64_8:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    crc32b %sil, %edi # sched: [3:1.00]
-; SKYLAKE-NEXT:    crc32b (%rdx), %edi # sched: [7:1.00]
+; SKYLAKE-NEXT:    crc32b (%rdx), %edi # sched: [8:1.00]
 ; SKYLAKE-NEXT:    movq %rdi, %rax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -264,7 +264,7 @@ define i64 @crc32_64_64(i64 %a0, i64 %a1
 ; SKYLAKE-LABEL: crc32_64_64:
 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    crc32q %rsi, %rdi # sched: [3:1.00]
-; SKYLAKE-NEXT:    crc32q (%rdx), %rdi # sched: [7:1.00]
+; SKYLAKE-NEXT:    crc32q (%rdx), %rdi # sched: [8:1.00]
 ; SKYLAKE-NEXT:    movq %rdi, %rax # sched: [1:0.25]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -503,9 +503,9 @@ define i32 @test_pcmpistri(<16 x i8> %a0
 ;
 ; SKYLAKE-LABEL: test_pcmpistri:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [11:3.00]
+; SKYLAKE-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [10:3.00]
 ; SKYLAKE-NEXT:    movl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [11:3.00]
+; SKYLAKE-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [10:3.00]
 ; SKYLAKE-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<def>
 ; SKYLAKE-NEXT:    leal (%rcx,%rax), %eax # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
@@ -562,8 +562,8 @@ define <16 x i8> @test_pcmpistrm(<16 x i
 ;
 ; SKYLAKE-LABEL: test_pcmpistrm:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [11:3.00]
-; SKYLAKE-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [11:3.00]
+; SKYLAKE-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [10:3.00]
+; SKYLAKE-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [10:3.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpistrm:
@@ -611,8 +611,8 @@ define <2 x i64> @test_pcmpgtq(<2 x i64>
 ;
 ; SKYLAKE-LABEL: test_pcmpgtq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKYLAKE-NEXT:    vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pcmpgtq:
@@ -661,8 +661,8 @@ define <2 x i64> @test_pclmulqdq(<2 x i6
 ;
 ; SKYLAKE-LABEL: test_pclmulqdq:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [11:2.00]
-; SKYLAKE-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [11:2.00]
+; SKYLAKE-NEXT:    vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [6:1.00]
+; SKYLAKE-NEXT:    vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pclmulqdq:

Modified: llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll?rev=313613&r1=313612&r2=313613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll Mon Sep 18 23:19:27 2017
@@ -48,9 +48,9 @@ define <16 x i8> @test_pabsb(<16 x i8> %
 ;
 ; SKYLAKE-LABEL: test_pabsb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpabsb %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpabsb %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpabsb (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pabsb:
@@ -113,9 +113,9 @@ define <4 x i32> @test_pabsd(<4 x i32> %
 ;
 ; SKYLAKE-LABEL: test_pabsd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpabsd %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpabsd %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpabsd (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pabsd:
@@ -178,9 +178,9 @@ define <8 x i16> @test_pabsw(<8 x i16> %
 ;
 ; SKYLAKE-LABEL: test_pabsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpabsw %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpabsw %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpabsw (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT:    vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pabsw:
@@ -626,8 +626,8 @@ define <8 x i16> @test_pmaddubsw(<16 x i
 ;
 ; SKYLAKE-LABEL: test_pmaddubsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmaddubsw:
@@ -682,8 +682,8 @@ define <8 x i16> @test_pmulhrsw(<8 x i16
 ;
 ; SKYLAKE-LABEL: test_pmulhrsw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT:    vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
+; SKYLAKE-NEXT:    vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT:    vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
 ; BTVER2-LABEL: test_pmulhrsw:
@@ -796,7 +796,7 @@ define <16 x i8> @test_psignb(<16 x i8>
 ;
 ; SKYLAKE-LABEL: test_psignb:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsignb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -855,7 +855,7 @@ define <4 x i32> @test_psignd(<4 x i32>
 ;
 ; SKYLAKE-LABEL: test_psignd:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsignd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;
@@ -914,7 +914,7 @@ define <8 x i16> @test_psignw(<8 x i16>
 ;
 ; SKYLAKE-LABEL: test_psignw:
 ; SKYLAKE:       # BB#0:
-; SKYLAKE-NEXT:    vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT:    vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
 ; SKYLAKE-NEXT:    vpsignw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
 ; SKYLAKE-NEXT:    retq # sched: [2:1.00]
 ;