[llvm] r313558 - [X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of sub_8bit
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 18 12:21:21 PDT 2017
Author: ctopper
Date: Mon Sep 18 12:21:21 2017
New Revision: 313558
URL: http://llvm.org/viewvc/llvm-project?rev=313558&view=rev
Log:
[X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of sub_8bit
This is similar to D37843, but for sub_8bit. This fixes all of the patterns except for the 2 that emit only an EXTRACT_SUBREG. That causes a verifier error with global isel because global isel doesn't know to issue the ABCD when doing this extract on 32-bits targets.
Differential Revision: https://reviews.llvm.org/D37890
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86InstrCompiler.td
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=313558&r1=313557&r2=313558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Sep 18 12:21:21 2017
@@ -2520,22 +2520,9 @@ bool X86FastISel::X86SelectTrunc(const I
return true;
}
- bool KillInputReg = false;
- if (!Subtarget->is64Bit()) {
- // If we're on x86-32; we can't extract an i8 from a general register.
- // First issue a copy to GR16_ABCD or GR32_ABCD.
- const TargetRegisterClass *CopyRC =
- (SrcVT == MVT::i16) ? &X86::GR16_ABCDRegClass : &X86::GR32_ABCDRegClass;
- unsigned CopyReg = createResultReg(CopyRC);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
- TII.get(TargetOpcode::COPY), CopyReg).addReg(InputReg);
- InputReg = CopyReg;
- KillInputReg = true;
- }
-
// Issue an extract_subreg.
unsigned ResultReg = fastEmitInst_extractsubreg(MVT::i8,
- InputReg, KillInputReg,
+ InputReg, false,
X86::sub_8bit);
if (!ResultReg)
return false;
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=313558&r1=313557&r2=313558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Sep 18 12:21:21 2017
@@ -2931,19 +2931,6 @@ void X86DAGToDAGISel::Select(SDNode *Nod
SDValue Imm = CurDAG->getTargetConstant(Mask, dl, MVT::i8);
SDValue Reg = N0.getOperand(0);
- // On x86-32, only the ABCD registers have 8-bit subregisters.
- if (!Subtarget->is64Bit()) {
- const TargetRegisterClass *TRC;
- switch (N0.getSimpleValueType().SimpleTy) {
- case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
- case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
- default: llvm_unreachable("Unsupported TEST operand type!");
- }
- SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
- Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
- Reg.getValueType(), Reg, RC), 0);
- }
-
// Extract the l-register.
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
MVT::i8, Reg);
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=313558&r1=313557&r2=313558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Mon Sep 18 12:21:21 2017
@@ -1399,16 +1399,11 @@ def : Pat<(and GR32:$src1, 0xffff),
(MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
// r & (2^8-1) ==> movz
def : Pat<(and GR32:$src1, 0xff),
- (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
- GR32_ABCD)),
- sub_8bit))>,
- Requires<[Not64BitMode]>;
+ (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>;
// r & (2^8-1) ==> movz
def : Pat<(and GR16:$src1, 0xff),
- (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
- (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
- sub_16bit)>,
- Requires<[Not64BitMode]>;
+ (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)),
+ sub_16bit)>;
// r & (2^32-1) ==> movz
def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
@@ -1425,15 +1420,6 @@ def : Pat<(and GR64:$src, 0xff),
(SUBREG_TO_REG (i64 0),
(MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
sub_32bit)>;
-// r & (2^8-1) ==> movz
-def : Pat<(and GR32:$src1, 0xff),
- (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
- Requires<[In64BitMode]>;
-// r & (2^8-1) ==> movz
-def : Pat<(and GR16:$src1, 0xff),
- (EXTRACT_SUBREG (MOVZX32rr8 (i8
- (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
- Requires<[In64BitMode]>;
} // AddedComplexity = 1
@@ -1441,16 +1427,11 @@ def : Pat<(and GR16:$src1, 0xff),
def : Pat<(sext_inreg GR32:$src, i16),
(MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
def : Pat<(sext_inreg GR32:$src, i8),
- (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
- GR32_ABCD)),
- sub_8bit))>,
- Requires<[Not64BitMode]>;
+ (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>;
def : Pat<(sext_inreg GR16:$src, i8),
- (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
- (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
- sub_16bit)>,
- Requires<[Not64BitMode]>;
+ (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)),
+ sub_16bit)>;
def : Pat<(sext_inreg GR64:$src, i32),
(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
@@ -1458,13 +1439,6 @@ def : Pat<(sext_inreg GR64:$src, i16),
(MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
def : Pat<(sext_inreg GR64:$src, i8),
(MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
-def : Pat<(sext_inreg GR32:$src, i8),
- (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
- Requires<[In64BitMode]>;
-def : Pat<(sext_inreg GR16:$src, i8),
- (EXTRACT_SUBREG (MOVSX32rr8
- (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
- Requires<[In64BitMode]>;
// sext, sext_load, zext, zext_load
def: Pat<(i16 (sext GR8:$src)),
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