[PATCH] D37975: [X86][SSE] Improve support for vselect(Cond, 0, X) -> ANDN(Cond, X)

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: lib/Target/X86/X86ISelLowering.cpp:30157-30159
+  // Cond value must be 'sign splat' to be converted to a logical op.
+  if (DAG.ComputeNumSignBits(Cond) != CondVT.getScalarSizeInBits())
+    return SDValue();
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We might be able to remove the legality checks below here now that we have this, but I agree that the bigger cleanup is to make this semi-generic in DAGCombiner, so x86 won't need to do anything else for these patterns.


Repository:
  rL LLVM

https://reviews.llvm.org/D37975