[PATCH] D37968: [ARM] Fix for indexed dot product instruction descriptions

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added a comment.

> Where is the restriction that only the lower 16 registers are allowed? Can you test quad regs, too? Just to make it clear the lane issue.

It's in the pseudo-code:

  integer m = UInt(Vm<3:0>);
  integer index = UInt(M);

Normally that 'M' bit would be the high bit of Vm (as for Vd and Vn just above). Here it's used to encode the lane.


https://reviews.llvm.org/D37968