[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Haicheng Wu via Phabricator via llvm-commits]

haicheng updated this revision to Diff 115633.
haicheng added a comment.

Use Geoff's code.  Please take a look.


Repository:
  rL LLVM

https://reviews.llvm.org/D36104

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  test/CodeGen/AArch64/arm64-addr-type-promotion.ll
  test/CodeGen/AArch64/arm64-cse.ll
  test/CodeGen/AArch64/copy-zero-reg.ll
  test/CodeGen/AArch64/i128-fast-isel-fallback.ll

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