[PATCH] D29934: [RISCV 12/n] Codegen support for memory operations

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 115578.
asb marked 3 inline comments as done.
asb added a comment.

Update based on review comments (thanks!). This version of the patch also adds (and tests) support for sextload/zextload/anyextload of an i1 value.


https://reviews.llvm.org/D29934

Files:
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCVAsmPrinter.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.cpp
  lib/Target/RISCV/RISCVInstrInfo.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVMCInstLower.cpp
  lib/Target/RISCV/RISCVSubtarget.h
  test/CodeGen/RISCV/alu.ll
  test/CodeGen/RISCV/mem.ll
  test/CodeGen/RISCV/wide-mem.ll

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