[llvm] r313298 - AMDGPU: Fix violating constant bus restriction

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Thu Sep 14 13:54:29 2017
New Revision: 313298

URL: http://llvm.org/viewvc/llvm-project?rev=313298&view=rev
Log:
AMDGPU: Fix violating constant bus restriction

You can't use madmk/madmk if it already uses an SGPR input.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=313298&r1=313297&r2=313298&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Sep 14 13:54:29 2017
@@ -2150,9 +2150,8 @@ static int64_t getFoldableImm(const Mach
   const MachineFunction *MF = MO->getParent()->getParent()->getParent();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   auto Def = MRI.getUniqueVRegDef(MO->getReg());
-  if (Def && (Def->getOpcode() == AMDGPU::S_MOV_B32 ||
-              Def->getOpcode() == AMDGPU::V_MOV_B32_e32) &&
-     Def->getOperand(1).isImm())
+  if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
+      Def->getOperand(1).isImm())
     return Def->getOperand(1).getImm();
   return AMDGPU::NoRegister;
 }
@@ -2194,7 +2193,9 @@ MachineInstr *SIInstrInfo::convertToThre
   const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
   const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
 
-  if (!Src0Mods && !Src1Mods && !Clamp && !Omod) {
+  if (!Src0Mods && !Src1Mods && !Clamp && !Omod &&
+      // If we have an SGPR input, we will violate the constant bus restriction.
+      !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg())) {
     if (auto Imm = getFoldableImm(Src2)) {
       return BuildMI(*MBB, MI, MI.getDebugLoc(),
                      get(IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32))

Modified: llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir?rev=313298&r1=313297&r2=313298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir Thu Sep 14 13:54:29 2017
@@ -108,3 +108,25 @@ body:             |
     %1 = V_MOV_B32_e32 1078523331, implicit %exec
     %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit %exec
 ...
+
+# Make sure constant bus restriction isn't violated if src0 is an SGPR.
+
+# GCN-LABEL: name: test_madak_sgpr_src0_f32
+# GCN: %1 = V_MOV_B32_e32 1078523331, implicit %exec
+# GCN: %2 = V_MAD_F32 0, killed %0, 0, %1, 0, %3, 0, 0, implicit %exec
+
+---
+name:            test_madak_sgpr_src0_f32
+registers:
+  - { id: 0, class: sreg_32_xm0 }
+  - { id: 1, class: vgpr_32}
+  - { id: 2, class: vgpr_32 }
+  - { id: 3, class: vgpr_32 }
+body:             |
+  bb.0:
+
+    %0 = IMPLICIT_DEF
+    %1 = V_MOV_B32_e32 1078523331, implicit %exec
+    %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit %exec
+
+...