[llvm] r313257 - [Hexagon] Make getMemAccessSize return size in bytes
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 14 05:06:41 PDT 2017
Author: kparzysz
Date: Thu Sep 14 05:06:40 2017
New Revision: 313257
URL: http://llvm.org/viewvc/llvm-project?rev=313257&view=rev
Log:
[Hexagon] Make getMemAccessSize return size in bytes
It used to return the actual field value from the instruction descriptor.
There is no reason for that, that value is not interesting in any way and
the specifics of its encoding in the descriptor should not be exposed.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Thu Sep 14 05:06:40 2017
@@ -2103,7 +2103,7 @@ void HexagonFrameLowering::optimizeSpill
}
if (!Bad) {
// Check sizes.
- unsigned S = (1U << (HII.getMemAccessSize(In) - 1));
+ unsigned S = HII.getMemAccessSize(In);
if (SI.Size != 0 && SI.Size != S)
Bad = true;
else
@@ -2312,7 +2312,7 @@ void HexagonFrameLowering::optimizeSpill
MachineInstr *CopyOut = nullptr;
if (DstR != FoundR) {
DebugLoc DL = MI.getDebugLoc();
- unsigned MemSize = (1U << (HII.getMemAccessSize(MI) - 1));
+ unsigned MemSize = HII.getMemAccessSize(MI);
assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
unsigned CopyOpc = TargetOpcode::COPY;
if (HII.isSignExtendingLoad(MI))
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Thu Sep 14 05:06:40 2017
@@ -24,14 +24,15 @@ class MemAccessSize<bits<4> value> {
bits<4> Value = value;
}
-// MemAccessSize is represented as 1+log2(N) where N is size in bits.
-def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction.
-def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
-def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
-def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
-def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
-def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
-def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
+// These numbers must match the MemAccessSize enumeration values in
+// HexagonBaseInfo.h.
+def NoMemAccess : MemAccessSize<0>;
+def ByteAccess : MemAccessSize<1>;
+def HalfWordAccess : MemAccessSize<2>;
+def WordAccess : MemAccessSize<3>;
+def DoubleWordAccess : MemAccessSize<4>;
+def Vector64Access : MemAccessSize<5>;
+def Vector128Access : MemAccessSize<6>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu Sep 14 05:06:40 2017
@@ -1706,8 +1706,8 @@ bool HexagonInstrInfo::areMemAccessesTri
return false;
// Get the access sizes.
- unsigned SizeA = (1u << (getMemAccessSize(MIa) - 1));
- unsigned SizeB = (1u << (getMemAccessSize(MIb) - 1));
+ unsigned SizeA = getMemAccessSize(MIa);
+ unsigned SizeB = getMemAccessSize(MIb);
// Get the offsets. Handle immediates only for now.
const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
@@ -2964,16 +2964,7 @@ unsigned HexagonInstrInfo::getBaseAndOff
!isMemOp(MI) && !isPostIncrement(MI))
return 0;
- // Since it is a memory access instruction, getMemAccessSize() should never
- // return 0.
- assert (getMemAccessSize(MI) &&
- "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
-
- // Return Values of getMemAccessSize() are
- // 0 - Checked in the assert above.
- // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
- // MemAccessSize is represented as 1+log2(N) where N is size in bits.
- AccessSize = (1U << (getMemAccessSize(MI) - 1));
+ AccessSize = getMemAccessSize(MI);
unsigned BasePos = 0, OffsetPos = 0;
if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
@@ -4001,8 +3992,22 @@ int HexagonInstrInfo::getMaxValue(const
}
unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
+ using namespace HexagonII;
const uint64_t F = MI.getDesc().TSFlags;
- return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
+ unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
+ unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
+ if (Size != 0)
+ return Size;
+
+ // Handle vector access sizes.
+ switch (S) {
+ case HexagonII::Vector64Access:
+ return 64;
+ case HexagonII::Vector128Access:
+ return 128;
+ default:
+ llvm_unreachable("Unexpected instruction");
+ }
}
// Returns the min value that doesn't need to be extended.
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Thu Sep 14 05:06:40 2017
@@ -45,16 +45,14 @@ namespace HexagonII {
PostInc = 6 // Post increment addressing mode
};
- // MemAccessSize is represented as 1+log2(N) where N is size in bits.
- enum class MemAccessSize {
- NoMemAccess = 0, // Not a memory access instruction.
- ByteAccess = 1, // Byte access instruction (memb).
- HalfWordAccess = 2, // Half word access instruction (memh).
- WordAccess = 3, // Word access instruction (memw).
- DoubleWordAccess = 4, // Double word access instruction (memd)
- // 5, // We do not have a 16 byte vector access.
- Vector64Access = 7, // 64 Byte vector access instruction (vmem).
- Vector128Access = 8 // 128 Byte vector access instruction (vmem).
+ enum MemAccessSize {
+ NoMemAccess = 0,
+ ByteAccess,
+ HalfWordAccess,
+ WordAccess,
+ DoubleWordAccess,
+ Vector64Access,
+ Vector128Access
};
// MCInstrDesc TSFlags
@@ -263,6 +261,16 @@ namespace HexagonII {
INST_ICLASS_ALU32_3 = 0xf0000000
};
+ LLVM_ATTRIBUTE_UNUSED
+ static unsigned getMemAccessSizeInBytes(MemAccessSize S) {
+ switch (S) {
+ case ByteAccess: return 1;
+ case HalfWordAccess: return 2;
+ case WordAccess: return 4;
+ case DoubleWordAccess: return 8;
+ default: return 0;
+ }
+ }
} // end namespace HexagonII
} // end namespace llvm
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp Thu Sep 14 05:06:40 2017
@@ -290,14 +290,14 @@ Hexagon::Fixups HexagonMCCodeEmitter::ge
++ImpUses) {
if (*ImpUses != Hexagon::GP)
continue;
- switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
- case HexagonII::MemAccessSize::ByteAccess:
+ switch (HexagonMCInstrInfo::getMemAccessSize(MCII, MI)) {
+ case 1:
return fixup_Hexagon_GPREL16_0;
- case HexagonII::MemAccessSize::HalfWordAccess:
+ case 2:
return fixup_Hexagon_GPREL16_1;
- case HexagonII::MemAccessSize::WordAccess:
+ case 4:
return fixup_Hexagon_GPREL16_2;
- case HexagonII::MemAccessSize::DoubleWordAccess:
+ case 8:
return fixup_Hexagon_GPREL16_3;
default:
raise_relocation_error(0, kind);
@@ -491,17 +491,17 @@ unsigned HexagonMCCodeEmitter::getExprOp
++ImpUses) {
if (*ImpUses != Hexagon::GP)
continue;
- switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
- case HexagonII::MemAccessSize::ByteAccess:
+ switch (HexagonMCInstrInfo::getMemAccessSize(MCII, MI)) {
+ case 1:
FixupKind = fixup_Hexagon_GPREL16_0;
break;
- case HexagonII::MemAccessSize::HalfWordAccess:
+ case 2:
FixupKind = fixup_Hexagon_GPREL16_1;
break;
- case HexagonII::MemAccessSize::WordAccess:
+ case 4:
FixupKind = fixup_Hexagon_GPREL16_2;
break;
- case HexagonII::MemAccessSize::DoubleWordAccess:
+ case 8:
FixupKind = fixup_Hexagon_GPREL16_3;
break;
default:
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Thu Sep 14 05:06:40 2017
@@ -226,12 +226,11 @@ void HexagonMCInstrInfo::extendIfNeeded(
addConstExtender(Context, MCII, MCB, MCI);
}
-HexagonII::MemAccessSize
-HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
- const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
-
- return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
- HexagonII::MemAccesSizeMask));
+unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII,
+ MCInst const &MCI) {
+ uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+ unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
+ return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
}
MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h?rev=313257&r1=313256&r2=313257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h Thu Sep 14 05:06:40 2017
@@ -31,12 +31,6 @@ class MCInstrDesc;
class MCInstrInfo;
class MCSubtargetInfo;
-namespace HexagonII {
-
-enum class MemAccessSize;
-
-} // end namespace HexagonII
-
class DuplexCandidate {
public:
unsigned packetIndexI, packetIndexJ, iClass;
@@ -123,9 +117,9 @@ MCInst const *extenderForIndex(MCInst co
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
MCInst const &MCI);
-// Return memory access size
-HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
- MCInst const &MCI);
+// Return memory access size in bytes
+unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
+
MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
// Return which duplex group this instruction belongs to
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