[llvm] r313254 - [mips] Pick the right variant of DINS upfront and enable target instruction verification
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 14 03:58:00 PDT 2017
Author: sdardis
Date: Thu Sep 14 03:58:00 2017
New Revision: 313254
URL: http://llvm.org/viewvc/llvm-project?rev=313254&view=rev
Log:
[mips] Pick the right variant of DINS upfront and enable target instruction verification
This patch complements D16810 "[mips] Make isel select the correct DEXT variant
up front.". Now ISel picks the right variant of DINS, so now there is no need
to replace DINS with the appropriate variant during
MipsMCCodeEmitter::encodeInstruction().
This patch also enables target specific instruction verification for ins, dins,
dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that
are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these
constraints are not checked during instruction selection. Adding machine
verification should catch outstanding cases.
Finally, correct a bug that instruction verification uncovered, where the
position operand of a DINSU generated during lowering was being silently
and accidently corrected to the correct value.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D34809
Added:
llvm/trunk/test/CodeGen/Mips/instverify/
llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir
llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir
llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir
Modified:
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/Mips/dins.ll
llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll
llvm/trunk/test/CodeGen/Mips/fcopysign.ll
llvm/trunk/test/CodeGen/Mips/mips64-f128.ll
llvm/trunk/test/CodeGen/Mips/mips64extins.ll
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Thu Sep 14 03:58:00 2017
@@ -101,33 +101,6 @@ static void LowerLargeShift(MCInst& Inst
}
}
-// Pick a DINS instruction variant based on the pos and size operands
-static void LowerDins(MCInst& InstIn) {
- assert(InstIn.getNumOperands() == 5 &&
- "Invalid no. of machine operands for DINS!");
-
- assert(InstIn.getOperand(2).isImm());
- int64_t pos = InstIn.getOperand(2).getImm();
- assert(InstIn.getOperand(3).isImm());
- int64_t size = InstIn.getOperand(3).getImm();
-
- assert((pos + size) <= 64 &&
- "DINS cannot have position plus size over 64");
- if (pos < 32) {
- if ((pos + size) > 0 && (pos + size) <= 32)
- return; // DINS, do nothing
- else if ((pos + size) > 32) {
- //DINSM
- InstIn.getOperand(3).setImm(size - 32);
- InstIn.setOpcode(Mips::DINSM);
- }
- } else if ((pos + size) > 32 && (pos + size) <= 64) {
- // DINSU
- InstIn.getOperand(2).setImm(pos - 32);
- InstIn.setOpcode(Mips::DINSU);
- }
-}
-
// Fix a bad compact branch encoding for beqc/bnec.
void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
// Encoding may be illegal !(rs < rt), but this situation is
@@ -211,10 +184,6 @@ encodeInstruction(const MCInst &MI, raw_
case Mips::DROTR_MM64R6:
LowerLargeShift(TmpInst);
break;
- // Double extract instruction is chosen by pos and size operands
- case Mips::DINS:
- LowerDins(TmpInst);
- break;
// Compact branches, enforce encoding restrictions.
case Mips::BEQC:
case Mips::BNEC:
Modified: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td Thu Sep 14 03:58:00 2017
@@ -164,10 +164,12 @@ class DCLZ_MM64R6_DESC {
}
class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
- uimm5_inssize_plus1, MipsIns>;
-class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
+ uimm5_inssize_plus1, immZExt5Plus32,
+ immZExt5Plus1, MipsIns>;
+class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
+ immZExt5, immZExtRange2To64, MipsIns>;
class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
- MipsIns>;
+ immZExt5, immZExt5Plus1, MipsIns>;
class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd,
II_DMTC0>;
class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Sep 14 03:58:00 2017
@@ -884,7 +884,8 @@ let DecoderNamespace = "MicroMips", Pred
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
- MipsIns>, EXT_FM_MM<0x0c>;
+ immZExt5, immZExt5Plus1, MipsIns>,
+ EXT_FM_MM<0x0c>;
/// Jump Instructions
let DecoderMethod = "DecodeJumpTargetMM" in {
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Sep 14 03:58:00 2017
@@ -327,11 +327,13 @@ let AdditionalPredicates = [NotInMicroMi
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
ISA_MIPS64R2;
- def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>,
- EXT_FM<7>, ISA_MIPS64R2;
- def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
+ def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, immZExt5,
+ immZExt5Plus1, MipsIns>, EXT_FM<7>, ISA_MIPS64R2;
+ def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1,
+ immZExt5Plus32, immZExt5Plus1, MipsIns>,
EXT_FM<6>, ISA_MIPS64R2;
- def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>,
+ def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
+ immZExt5, immZExtRange2To64, MipsIns>,
EXT_FM<5>, ISA_MIPS64R2;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Sep 14 03:58:00 2017
@@ -531,3 +531,90 @@ bool MipsInstrInfo::findCommutedOpIndice
}
return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
}
+
+// ins, ext, dext*, dins have the following constraints:
+// 0 <= pos < X
+// 0 < size <= X
+// 0 < pos+size <= x
+//
+// dinsm and dinsm have the following contraints:
+// 0 <= pos < X
+// 0 <= size <= X
+// 0 < pos+size <= x
+
+static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
+ const int64_t PosLow, const int64_t PosHigh,
+ const int64_t SizeLow,
+ const int64_t SizeHigh,
+ const int64_t BothLow,
+ const int64_t BothHigh) {
+ MachineOperand MOPos = MI.getOperand(2);
+ if (!MOPos.isImm()) {
+ ErrInfo = "Position is not an immediate!";
+ return false;
+ }
+ int64_t Pos = MOPos.getImm();
+ if (!((PosLow <= Pos) && (Pos < PosHigh))) {
+ ErrInfo = "Position operand is out of range!";
+ return false;
+ }
+
+ MachineOperand MOSize = MI.getOperand(3);
+ if (!MOSize.isImm()) {
+ ErrInfo = "Size operand is not an immediate!";
+ return false;
+ }
+ int64_t Size = MOSize.getImm();
+ if (!((SizeLow < Size) && (Size <= SizeHigh))) {
+ ErrInfo = "Size operand is out of range!";
+ return false;
+ }
+
+ if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
+ ErrInfo = "Position + Size is out of range!";
+ return false;
+ }
+
+ return true;
+}
+
+// Perform target specific instruction verification.
+bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
+ StringRef &ErrInfo) const {
+ // Verify that ins and ext instructions are well formed.
+ switch (MI.getOpcode()) {
+ case Mips::EXT:
+ case Mips::EXT_MM:
+ case Mips::INS:
+ case Mips::INS_MM:
+ case Mips::DINS:
+ case Mips::DINS_MM64R6:
+ return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
+ case Mips::DINSM:
+ case Mips::DINSM_MM64R6:
+ // The ISA spec has a subtle difference here in that it says:
+ // 2 <= size <= 64 for 'dinsm', so we change the bounds so that it
+ // is in line with the rest of instructions.
+ return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
+ case Mips::DINSU:
+ case Mips::DINSU_MM64R6:
+ // The ISA spec has a subtle difference here in that it says:
+ // 2 <= size <= 64 for 'dinsm', so we change the bounds so that it
+ // is in line with the rest of instructions.
+ return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 1, 32, 32, 64);
+ case Mips::DEXT:
+ case Mips::DEXT_MM64R6:
+ return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
+ case Mips::DEXTM:
+ case Mips::DEXTM_MM64R6:
+ return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
+ case Mips::DEXTU:
+ case Mips::DEXTU_MM64R6:
+ return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
+ default:
+ return true;
+ }
+
+ return true;
+}
+
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Thu Sep 14 03:58:00 2017
@@ -148,6 +148,10 @@ public:
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2) const override;
+ /// Perform target specific instruction verification.
+ bool verifyInstruction(const MachineInstr &MI,
+ StringRef &ErrInfo) const override;
+
protected:
bool isZeroImm(const MachineOperand &op) const;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Sep 14 03:58:00 2017
@@ -1205,6 +1205,11 @@ def immSExt16Plus1 : PatLeaf<(imm), [{
return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
}]>;
+def immZExtRange2To64 : PatLeaf<(imm), [{
+ return isUInt<7>(N->getZExtValue()) && (N->getZExtValue() >= 2) &&
+ (N->getZExtValue() <= 64);
+}]>;
+
// Mips Address Mode! SDNode frameindex could possibily be a match
// since load and store instructions from stack used it.
def addr :
@@ -1676,10 +1681,11 @@ class ExtBase<string opstr, RegisterOper
FrmR, opstr>, ISA_MIPS32R2;
class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
- Operand SizeOpnd, SDPatternOperator Op = null_frag>:
+ Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm,
+ SDPatternOperator Op = null_frag>:
InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
!strconcat(opstr, " $rt, $rs, $pos, $size"),
- [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
+ [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size, RO:$src))],
II_INS, FrmR, opstr>, ISA_MIPS32R2 {
let Constraints = "$src = $rt";
}
@@ -2183,7 +2189,8 @@ let AdditionalPredicates = [NotInMicroMi
immZExt5, immZExt5Plus1, MipsExt>,
EXT_FM<0>;
def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,
- uimm5_inssize_plus1, MipsIns>,
+ uimm5_inssize_plus1, immZExt5,
+ immZExt5Plus1, MipsIns>,
EXT_FM<4>;
}
/// Move Control Registers From/To CPU Registers
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Thu Sep 14 03:58:00 2017
@@ -1188,9 +1188,12 @@ bool MipsSEDAGToDAGISel::trySelect(SDNod
// The obvious "missing" case is when both are zero, but that case is
// handled by the ldi case.
if (ResNonZero) {
+ IntegerType *Int32Ty =
+ IntegerType::get(MF->getFunction()->getContext(), 32);
+ const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
- CurDAG->getTargetConstant(64, DL, MVT::i32),
- CurDAG->getTargetConstant(32, DL, MVT::i32),
+ CurDAG->getConstant(*Const32, DL, MVT::i32),
+ CurDAG->getConstant(*Const32, DL, MVT::i32),
SDValue(Res, 0)};
Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
Modified: llvm/trunk/test/CodeGen/Mips/dins.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dins.ll?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/dins.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/dins.ll Thu Sep 14 03:58:00 2017
@@ -58,13 +58,13 @@ entry:
; CHECK-LABEL: f123:
; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 123
-; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37
+; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37
; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 4
; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6
; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5
-; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14
+; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14
; MIPS64R2: dsrl $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50
-; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16
+; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16
; MIPS32R2: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 16
; MIPS32R2-NOT: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 18, 46
; MIPS16-NOT: ins{{[[:space:]].*}}
Modified: llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll Thu Sep 14 03:58:00 2017
@@ -48,7 +48,7 @@ entry:
; 64: dmtc1 $[[OR]], $f0
; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
-; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
+; 64R2: dinsu $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
; 64R2: dmtc1 $[[INS]], $f0
%add = fadd double %d, 1.000000e+00
Modified: llvm/trunk/test/CodeGen/Mips/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign.ll?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcopysign.ll Thu Sep 14 03:58:00 2017
@@ -28,8 +28,8 @@ entry:
; 64: dmtc1 $[[OR]], $f0
; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
-; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
-; 64R2: dmtc1 $[[INS]], $f0
+; 64R2: dinsu $[[INS:[0-9]+]], $[[EXT]], 63, 1
+; 64R2: dmtc1 $[[INS]], $f0
%call = tail call double @copysign(double %d0, double %d1) nounwind readnone
ret double %call
Added: llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 0..31
+---
+name: dext
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXT %0, 55, 10
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 0..32
+---
+name: dext
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXT %0, 5, 50
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 32..64
+---
+name: dextm
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXTM %0, 3, 62
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 0..31
+---
+name: dextm
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXTM %0, 65, 5
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 32..64
+---
+name: dextm
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXTM %0, 31, 67
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 32..64
+---
+name: dextu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXTU %0, 43, 30
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 32..63
+---
+name: dextu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXTU %0, 65, 5
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 0..32
+---
+name: dextu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DEXTU %0, 33, 67
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 0..32
+---
+name: dins
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINS %0, 17, 17
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 0..31
+---
+name: dins
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINS %0, 55, 10
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 0..32
+---
+name: dins
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINS %0, 5, 50
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 32..64
+---
+name: dinsu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINSM %0, 20, 50
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 0..31
+---
+name: dinsm
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINSM %0, 65, 5
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 2..64
+---
+name: dinsm
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINSM %0, 31, 67
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 32..64
+---
+name: dinsu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINSU %0, 50, 20
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 32..63
+---
+name: dinsu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINSU %0, 65, 5
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 0..32
+---
+name: dinsu
+alignment: 3
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr64, preferred-register: '' }
+ - { id: 1, class: gpr64, preferred-register: '' }
+liveins:
+ - { reg: '%a0_64', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0_64
+
+ %0 = COPY %a0_64
+ %1 = DINSU %0, 33, 67
+ %v0_64 = COPY %1
+ RetRA implicit %v0_64
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 0..32
+---
+name: f
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32, preferred-register: '' }
+ - { id: 1, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '%a0', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0
+
+ %0 = COPY %a0
+ %1 = EXT %0, 17, 17
+ %v0 = COPY %1
+ RetRA implicit %v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 0..31
+---
+name: f
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32, preferred-register: '' }
+ - { id: 1, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '%a0', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0
+
+ %0 = COPY %a0
+ %1 = EXT %0, 44, 21
+ %v0 = COPY %1
+ RetRA implicit %v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,49 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 0..32
+---
+name: f
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32, preferred-register: '' }
+ - { id: 1, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '%a0', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0
+
+ %0 = COPY %a0
+ %1 = EXT %0, 0, 33
+ %v0 = COPY %1
+ RetRA implicit %v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,54 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position + Size is out of range!
+
+# Check that the machine verifier checks the pos + size is in range 0..32
+---
+name: f
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32, preferred-register: '' }
+ - { id: 1, class: gpr32, preferred-register: '' }
+ - { id: 2, class: gpr32, preferred-register: '' }
+ - { id: 3, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '%a1', virtual-reg: '%1' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0, %a1
+
+ %1 = COPY %a1
+ %0 = COPY %a0
+ %2 = ANDi %1, 15
+ %3 = INS killed %2, 17, 17, %0
+ %v0 = COPY %3
+ RetRA implicit %v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,54 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Position operand is out of range!
+
+# Check that the machine verifier checks the position operand is in range 0..31
+---
+name: f
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32, preferred-register: '' }
+ - { id: 1, class: gpr32, preferred-register: '' }
+ - { id: 2, class: gpr32, preferred-register: '' }
+ - { id: 3, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '%a1', virtual-reg: '%1' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0, %a1
+
+ %1 = COPY %a1
+ %0 = COPY %a0
+ %2 = ANDi %1, 15
+ %3 = INS killed %2, 32, 4, %0
+ %v0 = COPY %3
+ RetRA implicit %v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir?rev=313254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir Thu Sep 14 03:58:00 2017
@@ -0,0 +1,54 @@
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+# CHECK: Size operand is out of range!
+
+# Check that the machine verifier checks the size operand is in range 0..32
+---
+name: f
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32, preferred-register: '' }
+ - { id: 1, class: gpr32, preferred-register: '' }
+ - { id: 2, class: gpr32, preferred-register: '' }
+ - { id: 3, class: gpr32, preferred-register: '' }
+liveins:
+ - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '%a1', virtual-reg: '%1' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.0.entry:
+ liveins: %a0, %a1
+
+ %1 = COPY %a1
+ %0 = COPY %a0
+ %2 = ANDi %1, 15
+ %3 = INS killed %2, 0, 40, %0
+ %v0 = COPY %3
+ RetRA implicit %v0
+
+...
Modified: llvm/trunk/test/CodeGen/Mips/mips64-f128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64-f128.ll?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64-f128.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64-f128.ll Thu Sep 14 03:58:00 2017
@@ -425,7 +425,7 @@ declare fp128 @llvm.powi.f128(fp128, i32
; NOT-R2R6-DAG: and $[[R4:[0-9]+]], $[[R1]], $[[R3]]
; ALL-DAG: ld $[[R5:[0-9]+]], %got_disp(gld0)
; ALL-DAG: ld $[[R6:[0-9]+]], 8($[[R5]])
-; R2R6: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 63, 1
+; R2R6: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 63, 1
; NOT-R2R6-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1
; NOT-R2R6-DAG: and $[[R8:[0-9]+]], $[[R6]], $[[R7]]
; NOT-R2R6-DAG: or $4, $[[R8]], $[[R4]]
Modified: llvm/trunk/test/CodeGen/Mips/mips64extins.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64extins.ll?rev=313254&r1=313253&r2=313254&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64extins.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64extins.ll Thu Sep 14 03:58:00 2017
@@ -41,7 +41,7 @@ entry:
define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
entry:
; CHECK-LABEL: dinsm:
-; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
+; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
%shl4 = shl i64 %j, 10
%and = and i64 %shl4, 8796093021184
%and5 = and i64 %i, -8796093021185
@@ -52,7 +52,7 @@ entry:
define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
entry:
; CHECK-LABEL: dinsu:
-; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
+; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
%shl4 = shl i64 %j, 40
%and = and i64 %shl4, 9006099743113216
%and5 = and i64 %i, -9006099743113217
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