[PATCH] D37017: [DAGCombiner] fold assertzexts separated by trunc

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: test/CodeGen/X86/negate-i1.ll:134
+; X64-NEXT:    negq %rdi
+; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    retq
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craig.topper wrote:
> efriedma wrote:
> > This seems kind of scary... is an "i1 zeroext" actually guaranteed to be zero-extended to 64 bits?
> Nope. It hit PR28540 which should be fixed by D37729
Should I make this patch dependent on that fix? Are we correct when we go from:
            t4: i32 = AssertZext t2, ValueType:ch:i8
          t5: i8 = truncate t4
        t7: i8 = AssertZext t5, ValueType:ch:i1
      t8: i1 = truncate t7
    t9: i64 = sign_extend t8

to:
        t16: i32 = AssertZext t2, ValueType:ch:i1
      t18: i64 = any_extend t16
    t15: i64 = sign_extend_inreg t18, ValueType:ch:i1



https://reviews.llvm.org/D37017