[llvm] r313149 - [mips] correct operand range for DINSM instruction

[Petar Jovanovic via llvm-commits]

Author: petarj
Date: Wed Sep 13 07:09:13 2017
New Revision: 313149

URL: http://llvm.org/viewvc/llvm-project?rev=313149&view=rev
Log:
[mips] correct operand range for DINSM instruction

This patch corrects the definition of the DINSM instruction.
Specification for DINSM instruction for Mips64 says that size operand should
be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives
range of 1 .. 32.

Patch by Aleksandar Beserminji.

Differential Revision: https://reviews.llvm.org/D37683

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/MC/Mips/mips64r2/valid.s
    llvm/trunk/test/MC/Mips/mips64r6/valid.s

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=313149&r1=313148&r2=313149&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Sep 13 07:09:13 2017
@@ -331,7 +331,7 @@ let AdditionalPredicates = [NotInMicroMi
              EXT_FM<7>, ISA_MIPS64R2;
   def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
               EXT_FM<6>, ISA_MIPS64R2;
-  def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>,
+  def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>,
               EXT_FM<5>, ISA_MIPS64R2;
 }
 

Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=313149&r1=313148&r2=313149&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Wed Sep 13 07:09:13 2017
@@ -106,6 +106,7 @@ a:
         deret
         di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
         di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        dinsm     $2,$3,4,34           # CHECK: dinsm $2, $3, 4, 34    # encoding: [0x7c,0x62,0x29,0x05]
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11

Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=313149&r1=313148&r2=313149&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Wed Sep 13 07:09:13 2017
@@ -114,6 +114,7 @@ a:
         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
         di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
+        dinsm   $2,$3,4,34       # CHECK: dinsm $2, $3, 4, 34    # encoding: [0x7c,0x62,0x29,0x05]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x95]