[llvm] r313135 - [GlobalISel][X86] support G_FPEXT operation.
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 13 02:05:23 PDT 2017
Author: ibreger
Date: Wed Sep 13 02:05:23 2017
New Revision: 313135
URL: http://llvm.org/viewvc/llvm-project?rev=313135&view=rev
Log:
[GlobalISel][X86] support G_FPEXT operation.
Summary: Support G_FPEXT operation. Selection done via TableGen'erated code.
Reviewers: zvi, guyblank, aymanmus, m_zuckerman
Reviewed By: zvi
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34816
Added:
llvm/trunk/test/CodeGen/X86/GlobalISel/fpext-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
Modified:
llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
Modified: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=313135&r1=313134&r2=313135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp Wed Sep 13 02:05:23 2017
@@ -170,6 +170,7 @@ void X86LegalizerInfo::setLegalizerInfoS
if (!Subtarget.hasSSE2())
return;
+ const LLT s32 = LLT::scalar(32);
const LLT s64 = LLT::scalar(64);
const LLT v16s8 = LLT::vector(16, 8);
const LLT v8s16 = LLT::vector(8, 16);
@@ -185,6 +186,9 @@ void X86LegalizerInfo::setLegalizerInfoS
setAction({BinOp, Ty}, Legal);
setAction({G_MUL, v8s16}, Legal);
+
+ setAction({G_FPEXT, s64}, Legal);
+ setAction({G_FPEXT, 1, s32}, Legal);
}
void X86LegalizerInfo::setLegalizerInfoSSE41() {
Modified: llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=313135&r1=313134&r2=313135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp Wed Sep 13 02:05:23 2017
@@ -182,10 +182,18 @@ X86RegisterBankInfo::getInstrMapping(con
}
unsigned NumOperands = MI.getNumOperands();
-
- // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
- getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
+
+ switch (Opc) {
+ case TargetOpcode::G_FPEXT:
+ // Instruction having only floating-point operands (all scalars in VECRReg)
+ getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
+ break;
+ default:
+ // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
+ getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
+ break;
+ }
// Finally construct the computed mapping.
SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/fpext-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/fpext-scalar.ll?rev=313135&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/fpext-scalar.ll (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/fpext-scalar.ll Wed Sep 13 02:05:23 2017
@@ -0,0 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=CHECK
+
+define double @test(float %a) {
+; CHECK-LABEL: test:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cvtss2sd %xmm0, %xmm0
+; CHECK-NEXT: retq
+entry:
+ %conv = fpext float %a to double
+ ret double %conv
+}
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir?rev=313135&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir Wed Sep 13 02:05:23 2017
@@ -0,0 +1,33 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
+--- |
+
+ define double @test(float %a) {
+ entry:
+ %conv = fpext float %a to double
+ ret double %conv
+ }
+
+...
+---
+name: test
+# ALL-LABEL: name: test
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+# ALL: %0(s32) = COPY %xmm0
+# ALL-NEXT: %1(s64) = G_FPEXT %0(s32)
+# ALL-NEXT: %xmm0 = COPY %1(s64)
+# ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1.entry:
+ liveins: %xmm0
+
+ %0(s32) = COPY %xmm0
+ %1(s64) = G_FPEXT %0(s32)
+ %xmm0 = COPY %1(s64)
+ RET 0, implicit %xmm0
+
+...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir?rev=313135&r1=313134&r2=313135&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir Wed Sep 13 02:05:23 2017
@@ -231,7 +231,12 @@
ret float %cond
}
-
+ define double @test_fpext(float %a) {
+ entry:
+ %conv = fpext float %a to double
+ ret double %conv
+ }
+
...
---
name: test_add_i8
@@ -1384,3 +1389,26 @@ body: |
RET 0, implicit %xmm0
...
+---
+name: test_fpext
+# CHECK-LABEL: name: test_fpext
+alignment: 4
+legalized: true
+regBankSelected: false
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+body: |
+ bb.1.entry:
+ liveins: %xmm0
+
+ %0(s32) = COPY %xmm0
+ %1(s64) = G_FPEXT %0(s32)
+ %xmm0 = COPY %1(s64)
+ RET 0, implicit %xmm0
+
+...
+
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir?rev=313135&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir Wed Sep 13 02:05:23 2017
@@ -0,0 +1,40 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
+--- |
+
+ define double @test(float %a) {
+ entry:
+ %conv = fpext float %a to double
+ ret double %conv
+ }
+
+...
+---
+name: test
+# ALL-LABEL: name: test
+alignment: 4
+legalized: true
+regBankSelected: true
+# ALL: registers:
+# ALL-NEXT: - { id: 0, class: fr32, preferred-register: '' }
+# ALL-NEXT: - { id: 1, class: fr64, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# ALL: %0 = COPY %xmm0
+# ALL-NEXT: %1 = CVTSS2SDrr %0
+# ALL-NEXT: %xmm0 = COPY %1
+# ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1.entry:
+ liveins: %xmm0
+
+ %0(s32) = COPY %xmm0
+ %1(s64) = G_FPEXT %0(s32)
+ %xmm0 = COPY %1(s64)
+ RET 0, implicit %xmm0
+
+...
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