[llvm] r313126 - [X86] Make sure we emit a SUBREG_TO_REG after the MOV32ri when creating a BEXTR64rr instruction from a shift/and pair.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed Sep 13 00:53:21 2017
New Revision: 313126

URL: http://llvm.org/viewvc/llvm-project?rev=313126&view=rev
Log:
[X86] Make sure we emit a SUBREG_TO_REG after the MOV32ri when creating a BEXTR64rr instruction from a shift/and pair.

Fixes PR34589.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/bmi.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=313126&r1=313125&r2=313126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Sep 13 00:53:21 2017
@@ -2337,8 +2337,15 @@ bool X86DAGToDAGISel::matchBEXTRFromAnd(
   if (!Subtarget->hasTBM()) {
     ROpc = NVT == MVT::i64 ? X86::BEXTR64rr : X86::BEXTR32rr;
     MOpc = NVT == MVT::i64 ? X86::BEXTR64rm : X86::BEXTR32rm;
-    SDNode *Move = CurDAG->getMachineNode(X86::MOV32ri, dl, NVT, New);
-    New = SDValue(Move, 0);
+    New = SDValue(CurDAG->getMachineNode(X86::MOV32ri, dl, NVT, New), 0);
+    if (NVT == MVT::i64) {
+      New =
+          SDValue(CurDAG->getMachineNode(
+                      TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
+                      CurDAG->getTargetConstant(0, dl, MVT::i64), New,
+                      CurDAG->getTargetConstant(X86::sub_32bit, dl, MVT::i32)),
+                  0);
+    }
   }
 
   MachineSDNode *NewNode;

Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=313126&r1=313125&r2=313126&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi.ll Wed Sep 13 00:53:21 2017
@@ -405,6 +405,18 @@ define i64 @bextr64c(i64 %x, i32 %y) {
   ret i64 %tmp1
 }
 
+define i64 @bextr64d(i64 %a) {
+; CHECK-LABEL: bextr64d:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl $8450, %eax # imm = 0x2102
+; CHECK-NEXT:    bextrq %rax, %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shr = lshr i64 %a, 2
+  %and = and i64 %shr, 8589934591
+  ret i64 %and
+}
+
 define i32 @non_bextr32(i32 %x) {
 ; CHECK-LABEL: non_bextr32:
 ; CHECK:       # BB#0: # %entry