[PATCH] D37775: Add a verifier test to check the access on both sides of COPY are the same
Aditya Nandakumar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 12 15:32:57 PDT 2017
aditya_nandakumar created this revision.
Herald added a subscriber: mgorny.
Only checks if there are no sub registers involved for now.
There are lots of failures currently which need to be fixed by various backends.
Splitting this off from https://reviews.llvm.org/D37640
Repository:
rL LLVM
https://reviews.llvm.org/D37775
Files:
lib/CodeGen/MachineVerifier.cpp
test/Verifier/test_copy.mir
unittests/CodeGen/CMakeLists.txt
unittests/IR/CMakeLists.txt
Index: unittests/IR/CMakeLists.txt
===================================================================
--- unittests/IR/CMakeLists.txt
+++ unittests/IR/CMakeLists.txt
@@ -2,6 +2,7 @@
Analysis
AsmParser
Core
+ GlobalISel
Support
Passes
)
Index: unittests/CodeGen/CMakeLists.txt
===================================================================
--- unittests/CodeGen/CMakeLists.txt
+++ unittests/CodeGen/CMakeLists.txt
@@ -2,6 +2,7 @@
AsmPrinter
CodeGen
Core
+ GlobalISel
Support
)
Index: test/Verifier/test_copy.mir
===================================================================
--- /dev/null
+++ test/Verifier/test_copy.mir
@@ -0,0 +1,30 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+--- |
+ ; ModuleID = 'test.ll'
+ source_filename = "test.ll"
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-unknown-unknown"
+
+ define i32 @test_copy(i32 %argc) {
+ ret i32 0
+ }
+
+...
+---
+name: test_copy
+legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+liveins:
+body: |
+ bb.0:
+ liveins: %w0
+ ; This test is used to catch verifier errors with copys having mismatching sizes
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
+
+ %0(s8) = COPY %w0
+...
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -49,6 +49,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
using namespace llvm;
namespace {
@@ -943,6 +944,21 @@
MI);
break;
}
+ case TargetOpcode::COPY: {
+ const MachineOperand &DstOp = MI->getOperand(0);
+ const MachineOperand &SrcOp = MI->getOperand(1);
+ unsigned DstSize =
+ RegisterBankInfo::getSizeInBits(DstOp.getReg(), *MRI, *TRI);
+ unsigned SrcSize =
+ RegisterBankInfo::getSizeInBits(SrcOp.getReg(), *MRI, *TRI);
+ if (DstSize != SrcSize)
+ // Catch only obvious cases not involving subregs for now.
+ if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
+ report("Copy Instruction is illegal with mismatching sizes", MI);
+ errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize << "\n";
+ }
+ break;
+ }
case TargetOpcode::STATEPOINT:
if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
!MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
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