[PATCH] D36795: [SystemZ] Increase number of LOCRs emitted by passing regalloc hints

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa added a comment.

>> It would have been nice to *guarantee* that the pseudo will get either high or low parts, like gcc will let you specify combinations of legal register operands. If that could be done, SystemZ could even remove its custom pass that handles any rare cases of mixed operands. But I suppose this would not be easy to do, or?
> 
> I didn't get what you would like to do.

I believe that in gcc it is possible to specify legal combinations in the .md file, something like (source-reg "GR32, GRH32"), (dst-reg "GR32, GRH32"). This would then be used during regalloc so that one of the two combinations would take effect (GR32/GR32 or GRH32/GRH32). This would be very nice in LLVM in this case, since regalloc would know what to do without hints, and it could also put a guarantee so that the target did not have to catch any bad cases after the fact. I guess I am just asking if there has been any effort or plan in this direction previously or what the best way of achieving this in LLVM might be.

BTW, in this particular case, it would be enough to say that "all operands of a single MI which are all GRX32 must be allocated to the same subclass: GR32 (low) or GRH32 (high)". Not sure if this is general enough to be considered for implementing - the gcc method seems more ideal.

Your suggestion of making non-hard-hints considered expensive (via a cost function for each register in the AllocationOrder?), makes sense to me though, especially if it would help in other contexts as well. This might make for an even better final result than only allowing the hard hints.


https://reviews.llvm.org/D36795