[PATCH] D37615: [AVR] implement the relocation of LDI and other Instructions for LLD
Leslie Zhai via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 11 23:57:34 PDT 2017
xiangzhai updated this revision to Diff 114764.
xiangzhai added a comment.
Dear Dylan,
How is going? long time no see :)
I updated my patch as your suggestion, and I follow your testcase <https://github.com/llvm-mirror/llvm/tree/master/test/MC/AVR> to cover all relocations, but I have no idea about:
1. R_AVR_LO8_LDI_GS
it equals to `R_AVR_LO8_LDI_PM`, so do I need to test it `lo8_ldi_gs`?
2. R_AVR_16_PM
3. R_AVR_LDS_STS_16
`sts foo, r25` failed to generate such reloc?
Could you give me some hint about how to cover such relocations for testcase? thanks a lot!
Dear Rui,
> Can you add more code to the test file so that all relocations are covered by the test? The number of relocations generated by the test is apparently less than the number of the relocations you are implementing in this patch.
Sorry that there are still 3 relocations without covering, I will find equal Instructions to generate them, I added more testcase to cover others:
$ avr-readelf -r basic-avr.o
Relocation section '.rela.text' at offset 0xdc contains 23 entries:
Offset Info Type Sym.Value Sym. Name + Addend
00000000 00000112 R_AVR_CALL 00000000 .text + 26
00000004 00000106 R_AVR_LO8_LDI 00000000 .text + 26
00000006 00000107 R_AVR_HI8_LDI 00000000 .text + 26
00000008 00000108 R_AVR_HH8_LDI 00000000 .text + 26
0000000a 00000116 R_AVR_MS8_LDI 00000000 .text + 26
0000000c 00000113 R_AVR_LDI 00000000 .text + 26
0000000e 00000109 R_AVR_LO8_LDI_NEG 00000000 .text + 26
00000010 0000010a R_AVR_HI8_LDI_NEG 00000000 .text + 26
00000012 0000010b R_AVR_HH8_LDI_NEG 00000000 .text + 26
00000014 00000117 R_AVR_MS8_LDI_NEG 00000000 .text + 26
00000016 0000010c R_AVR_LO8_LDI_PM 00000000 .text + 26
00000018 0000010d R_AVR_HI8_LDI_PM 00000000 .text + 26
0000001a 0000010e R_AVR_HH8_LDI_PM 00000000 .text + 26
0000001c 0000010f R_AVR_LO8_LDI_PM_NEG 00000000 .text + 26
0000001e 00000110 R_AVR_HI8_LDI_PM_NEG 00000000 .text + 26
00000020 00000111 R_AVR_HH8_LDI_PM_NEG 00000000 .text + 26
00000022 00000102 R_AVR_7_PCREL 00000000 .text + 26
00000024 00000103 R_AVR_13_PCREL 00000000 .text + 26
0000002e 00000114 R_AVR_6 00000000 .text + 26
00000032 00000104 R_AVR_16 00000000 .text + 26
00000034 00000122 R_AVR_PORT6 00000000 .text + 27
00000036 00000123 R_AVR_PORT5 00000000 .text + 0
00000038 00000115 R_AVR_6_ADIW 00000000 .text + 26
relocated by avr-ld:
$ avr-objdump -d basic-avr
basic-avr: file format elf32-avr
Disassembly of section .text:
00000000 <__ctors_end>:
0: 0e 94 13 00 call 0x26 ; 0x26 <foo>
4: 06 e2 ldi r16, 0x26 ; 38
6: 10 e0 ldi r17, 0x00 ; 0
8: 20 e0 ldi r18, 0x00 ; 0
a: 30 e0 ldi r19, 0x00 ; 0
c: 46 e2 ldi r20, 0x26 ; 38
e: 5a ed ldi r21, 0xDA ; 218
10: 6f ef ldi r22, 0xFF ; 255
12: 7f ef ldi r23, 0xFF ; 255
14: 8f ef ldi r24, 0xFF ; 255
16: 93 e1 ldi r25, 0x13 ; 19
18: a0 e0 ldi r26, 0x00 ; 0
1a: b0 e0 ldi r27, 0x00 ; 0
1c: cd ee ldi r28, 0xED ; 237
1e: df ef ldi r29, 0xFF ; 255
20: ef ef ldi r30, 0xFF ; 255
22: 09 f4 brne .+2 ; 0x26 <foo>
24: 00 c0 rjmp .+0 ; 0x26 <foo>
00000026 <foo>:
26: 2a 80 ldd r2, Y+2 ; 0x02
28: 08 80 ld r0, Y
2a: 94 84 ldd r9, Z+12 ; 0x0c
2c: 76 8c ldd r7, Z+30 ; 0x1e
2e: 96 a0 ldd r9, Z+38 ; 0x26
30: 00 91 26 00 lds r16, 0x0026 ; 0x800026 <__EEPROM_REGION_LENGTH__+0x7f0026>
34: 47 b5 in r20, 0x27 ; 39
36: 00 9a sbi 0x00, 0 ; 0
38: b6 96 adiw r30, 0x26 ; 38
equals to LLD:
$ avr-objdump -d basic-avr-lld
basic-avr-lld: file format elf32-avr
Disassembly of section .text:
00000000 <main>:
0: 0e 94 13 00 call 0x26 ; 0x26 <foo>
4: 06 e2 ldi r16, 0x26 ; 38
6: 10 e0 ldi r17, 0x00 ; 0
8: 20 e0 ldi r18, 0x00 ; 0
a: 30 e0 ldi r19, 0x00 ; 0
c: 46 e2 ldi r20, 0x26 ; 38
e: 5a ed ldi r21, 0xDA ; 218
10: 6f ef ldi r22, 0xFF ; 255
12: 7f ef ldi r23, 0xFF ; 255
14: 8f ef ldi r24, 0xFF ; 255
16: 93 e1 ldi r25, 0x13 ; 19
18: a0 e0 ldi r26, 0x00 ; 0
1a: b0 e0 ldi r27, 0x00 ; 0
1c: cd ee ldi r28, 0xED ; 237
1e: df ef ldi r29, 0xFF ; 255
20: ef ef ldi r30, 0xFF ; 255
22: 09 f4 brne .+2 ; 0x26 <foo>
24: 00 c0 rjmp .+0 ; 0x26 <foo>
00000026 <foo>:
26: 2a 80 ldd r2, Y+2 ; 0x02
28: 08 80 ld r0, Y
2a: 94 84 ldd r9, Z+12 ; 0x0c
2c: 76 8c ldd r7, Z+30 ; 0x1e
2e: 96 a0 ldd r9, Z+38 ; 0x26
30: 00 91 26 00 lds r16, 0x0026 ; 0x800026 <foo+0x800000>
34: 47 b5 in r20, 0x27 ; 39
36: 00 9a sbi 0x00, 0 ; 0
38: b6 96 adiw r30, 0x26 ; 38
Regards,
Leslie Zhai
Repository:
rL LLVM
https://reviews.llvm.org/D37615
Files:
ELF/Arch/AVR.cpp
test/ELF/basic-avr.s
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