[PATCH] D37294: [X86][Skylake] Adding the scheduling information for the SkylakeClient target

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Sorry to hijack this patch, but does anyone have any ideas how we can increase test coverage for the instructions we're now scheduling for? I've been slowly adding sse/avx/bmi instructions when I find the time (and I'm hoping to get fma/avx2 done soon) - those are time consuming to do but pretty trivial.

It's a lot trickier to ensure we have coverage for the various x86 core instructions, especially all the various cases of ancient x86 instructions, 8/16-bit integers, x87 etc. which are being included in these new models but not tested.

Would we be best off just adding support for instruction schedule comments to inline asm or is there a better way?


Repository:
  rL LLVM

https://reviews.llvm.org/D37294