[PATCH] D37673: [X86] Remove portions of r275950 that are no longer needed with i1 not being a legal type
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 10 21:38:52 PDT 2017
craig.topper updated this revision to Diff 114534.
craig.topper added a comment.
Remove a method declaration for the method that was deleted.
https://reviews.llvm.org/D37673
Files:
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
Index: lib/Target/X86/X86ISelLowering.h
===================================================================
--- lib/Target/X86/X86ISelLowering.h
+++ lib/Target/X86/X86ISelLowering.h
@@ -1203,8 +1203,6 @@
SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerToBT(SDValue And, ISD::CondCode CC, const SDLoc &dl,
- SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -16959,6 +16959,7 @@
/// Result of 'and' is compared against zero. Change to a BT node if possible.
static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
const SDLoc &dl, SelectionDAG &DAG) {
+ assert(And.getOpcode() == ISD::AND && "Expected AND node!");
SDValue Op0 = And.getOperand(0);
SDValue Op1 = And.getOperand(1);
if (Op0.getOpcode() == ISD::TRUNCATE)
@@ -17007,32 +17008,6 @@
return SDValue();
}
-// Convert (truncate (srl X, N) to i1) to (bt X, N)
-static SDValue LowerTruncateToBT(SDValue Op, ISD::CondCode CC,
- const SDLoc &dl, SelectionDAG &DAG) {
-
- assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
- "Expected TRUNCATE to i1 node");
-
- if (Op.getOperand(0).getOpcode() != ISD::SRL)
- return SDValue();
-
- SDValue ShiftRight = Op.getOperand(0);
- return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
- CC, dl, DAG);
-}
-
-/// Result of 'and' or 'trunc to i1' is compared against zero.
-/// Change to a BT node if possible.
-SDValue X86TargetLowering::LowerToBT(SDValue Op, ISD::CondCode CC,
- const SDLoc &dl, SelectionDAG &DAG) const {
- if (Op.getOpcode() == ISD::AND)
- return LowerAndToBT(Op, CC, dl, DAG);
- if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
- return LowerTruncateToBT(Op, CC, dl, DAG);
- return SDValue();
-}
-
/// Turns an ISD::CondCode into a value suitable for SSE floating-point mask
/// CMPs.
static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
@@ -17554,14 +17529,10 @@
// Lower (X & (1 << N)) == 0 to BT(X, N).
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
// Lower ((X >>s N) & 1) != 0 to BT(X, N).
- // Lower (trunc (X >> N) to i1) to BT(X, N).
- if (Op0.hasOneUse() && isNullConstant(Op1) &&
+ if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && isNullConstant(Op1) &&
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
- if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
- if (VT == MVT::i1)
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
+ if (SDValue NewSetCC = LowerAndToBT(Op0, CC, dl, DAG))
return NewSetCC;
- }
}
// Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
@@ -17935,7 +17906,7 @@
// We know the result of AND is compared against zero. Try to match
// it to BT.
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
- if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
+ if (SDValue NewSetCC = LowerAndToBT(Cond, ISD::SETNE, DL, DAG)) {
CC = NewSetCC.getOperand(0);
Cond = NewSetCC.getOperand(1);
AddTest = false;
@@ -18790,9 +18761,10 @@
if (isTruncWithZeroHighBitsInput(Cond, DAG))
Cond = Cond.getOperand(0);
- // We know the result is compared against zero. Try to match it to BT.
- if (Cond.hasOneUse()) {
- if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
+ // We know the result of AND is compared against zero. Try to match
+ // it to BT.
+ if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
+ if (SDValue NewSetCC = LowerAndToBT(Cond, ISD::SETNE, dl, DAG)) {
CC = NewSetCC.getOperand(0);
Cond = NewSetCC.getOperand(1);
addTest = false;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D37673.114534.patch
Type: text/x-patch
Size: 4322 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170911/bb50fef6/attachment.bin>
More information about the llvm-commits
mailing list