[llvm] r312724 - [ARM] Remove redundant vcvt patterns.

[Benjamin Kramer via llvm-commits]

Author: d0k
Date: Thu Sep  7 07:52:26 2017
New Revision: 312724

URL: http://llvm.org/viewvc/llvm-project?rev=312724&view=rev
Log:
[ARM] Remove redundant vcvt patterns.

These don't add any value as they're just compositions of existing
patterns. However, they can confuse the cost logic in ISel, leading to
duplicated vcvt instructions like in PR33199.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/test/CodeGen/ARM/vcvt.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=312724&r1=312723&r2=312724&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Sep  7 07:52:26 2017
@@ -1435,9 +1435,6 @@ def VTOSIZD : AVConv1IsD_Encode<0b11101,
 let Predicates=[HasVFP2, HasDPVFP] in {
   def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
                (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
-
-  def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
-               (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
 }
 
 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
@@ -1455,10 +1452,6 @@ def VTOSIZS : AVConv1InsS_Encode<0b11101
 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
                    (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
 
-def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
-                                   addrmode5:$ptr),
-                   (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
-
 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
                                  (outs SPR:$Sd), (ins SPR:$Sm),
                                  IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
@@ -1478,9 +1471,6 @@ def VTOUIZD : AVConv1IsD_Encode<0b11101,
 let Predicates=[HasVFP2, HasDPVFP] in {
   def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
                (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
-
-  def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
-               (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
 }
 
 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
@@ -1498,10 +1488,6 @@ def VTOUIZS : AVConv1InsS_Encode<0b11101
 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
                    (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
 
-def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
-                                   addrmode5:$ptr),
-                  (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
-
 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
                                  (outs SPR:$Sd), (ins SPR:$Sm),
                                  IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",

Modified: llvm/trunk/test/CodeGen/ARM/vcvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt.ll?rev=312724&r1=312723&r2=312724&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcvt.ll Thu Sep  7 07:52:26 2017
@@ -197,3 +197,22 @@ define <2 x i64> @fix_double_to_i64(<2 x
   ret <2 x i64> %conv
 }
 
+define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) {
+  %conv = fptosi double %c to i32
+  store i32 %conv, i32* %p, align 4
+  store i32 %conv, i32* %q, align 4
+  ret i32 %conv
+; CHECK-LABEL: multi_sint:
+; CHECK: vcvt.s32.f64
+; CHECK-NOT: vcvt
+}
+
+define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) {
+  %conv = fptoui double %c to i32
+  store i32 %conv, i32* %p, align 4
+  store i32 %conv, i32* %q, align 4
+  ret i32 %conv
+; CHECK-LABEL: multi_uint:
+; CHECK: vcvt.u32.f64
+; CHECK-NOT: vcvt
+}