[PATCH] D29933: [RISCV 11/n] Initial codegen support for ALU operations

[Mandeep Singh Grang via Phabricator via llvm-commits]

mgrang added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:45
+
+  // Compute derived properties from the register classes
+  computeRegisterProperties(STI.getRegisterInfo());
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Period at end of comment.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:66
+                                            SelectionDAG &DAG) const {
+  switch (Op.getOpcode()) {
+  default:
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This currently will always report error. I guess you intend to add more cases in future?


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:72
+
+// Calling Convention Implementation
+#include "RISCVGenCallingConv.inc"
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Period at end of comment.


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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:91
+
+  if (IsVarArg) {
+    report_fatal_error("VarArg not supported");
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I think it would be better to omit the braces in case there is a single statement inside if. Would make code more compact, no?

I had the same observation about your other RISCV patches. 


https://reviews.llvm.org/D29933