[PATCH] D37365: [x86] Enable f128 as a legal type in 64-bit mode if SSE is enabled rather than if MMX is enabled.

[Chih-Hung Hsieh via Phabricator via llvm-commits]

chh resigned from this revision.
chh added a comment.

My original change in lib/Target/X86/X86ISelLowering.cpp
was part of https://reviews.llvm.org/D15134 to fix
calling convention bug of f128 type mentioned in
https://bugs.llvm.org/show_bug.cgi?id=23897.

Android's x64 target assumes both -msse and -mmmx.
So it works with

  if (Subtarget.is64Bit() && Subtarget.hasMMX())

or

  if (Subtarget.is64Bit() && Subtarget.hasSSE1())

or

  if (Subtarget.is64Bit() && Subtarget.hasMMX() && Subtarget.hasSSE1())

I see now with -msse and -mno-mmx, gcc still uses %xmm0.
That seems to be compatible with AMD64 ABI, too.
So your change in X86ISelLowering.cpp:611 is good:

  if (Subtarget.is64Bit() && Subtarget.hasSSE1())

Could you change the 3 affected test files to include both
(1) original +mmx mode, (no sse) but expected output should be changed.
(2) add +sse mode, and the expected output is to using %xmm0 for __float128

The remaining big question is what to do with __float128 when there is no SSE.
I think gcc's output is still better matching AMD64 ABI.
Without SSE,

  gcc passes __float128 on stack, but reject source code that returns __float128.

$ gcc -S -O2 m.c -mno-sse -mno-mmx -o m.g.s

1. or gcc -S -O2 m.c -mno-sse -o m.g.mmx.s

m.c: In function 'get1':
m.c:5:1: error: SSE register return with SSE disabled
 __float128 get1() { return x; }
m.c:13:58: error: SSE register return with SSE disabled
 void foo(__float128 a, __float128 b, __float128 *c) { *c = a + b; }

It should take more changes (and maybe library functions) to make clang's output
match gcc's under -mno-sse.  We should fix that problem later in a separate CL.


https://reviews.llvm.org/D37365