[PATCH] D37516: [ARM] Implement isTruncateFree
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 6 07:31:04 PDT 2017
samparker created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.
Implement the isTruncateFree hooks, lifted from AArch64, that are used by TargetTransformInfo. This allows simplifycfg to reduce the test case into a single basic block.
https://reviews.llvm.org/D37516
Files:
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMISelLowering.h
test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll
Index: test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll
===================================================================
--- /dev/null
+++ test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll
@@ -0,0 +1,25 @@
+;RUN: opt -S -simplifycfg -mtriple=arm < %s | FileCheck %s
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+
+; CHECK-LABEL: select_trunc_i64
+; CHECK-NOT: br
+; CHECK: select
+; CHECK: select
+define arm_aapcscc i32 @select_trunc_i64(i32 %a, i32 %b) {
+entry:
+ %conv = sext i32 %a to i64
+ %conv1 = sext i32 %b to i64
+ %add = add nsw i64 %conv1, %conv
+ %cmp = icmp sgt i64 %add, 2147483647
+ br i1 %cmp, label %cond.end7, label %cond.false
+
+cond.false: ; preds = %entry
+ %0 = icmp sgt i64 %add, -2147483648
+ %cond = select i1 %0, i64 %add, i64 -2147483648
+ %extract.t = trunc i64 %cond to i32
+ br label %cond.end7
+
+cond.end7: ; preds = %cond.false, %entry
+ %cond8.off0 = phi i32 [ 2147483647, %entry ], [ %extract.t, %cond.false ]
+ ret i32 %cond8.off0
+}
Index: lib/Target/ARM/ARMISelLowering.h
===================================================================
--- lib/Target/ARM/ARMISelLowering.h
+++ lib/Target/ARM/ARMISelLowering.h
@@ -308,7 +308,8 @@
bool MemcpyStrSrc,
MachineFunction &MF) const override;
- using TargetLowering::isZExtFree;
+ bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
+ bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
bool isZExtFree(SDValue Val, EVT VT2) const override;
bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -12179,6 +12179,23 @@
return MVT::Other;
}
+bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
+ if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
+ return false;
+ unsigned NumBits1 = SrcTy->getPrimitiveSizeInBits();
+ unsigned NumBits2 = DstTy->getPrimitiveSizeInBits();
+ return NumBits1 > NumBits2;
+}
+
+bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
+ if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() ||
+ !DstVT.isInteger())
+ return false;
+ unsigned NumBits1 = SrcVT.getSizeInBits();
+ unsigned NumBits2 = DstVT.getSizeInBits();
+ return NumBits1 > NumBits2;
+}
+
bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
if (Val.getOpcode() != ISD::LOAD)
return false;
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