[PATCH] D37515: [mips] Generate memory dependencies for byVal arguments

[Stefan Maksimovic via Phabricator via llvm-commits]

smaksimovic created this revision.
Herald added a subscriber: arichardson.

There were no memory dependencies made between stores generated when lowering formal arguments and loads generated when call lowering byVal arguments which made the Post-RA scheduler place a load before a matching store.

- make the fixed object stored to mutable so that the load instructions can have their memory dependencies added
- make the MachinePointerInfo take no arguments which makes the underlying object for the stores and the loads match, i.e. point to a stack frame object instead of pointing to the function argument

This problem appeared when passing a byVal parameter coupled with a fastcc function call.


https://reviews.llvm.org/D37515

Files:
  lib/Target/Mips/MipsISelLowering.cpp
  test/CodeGen/Mips/fastcc_byval.ll


Index: test/CodeGen/Mips/fastcc_byval.ll
===================================================================
--- test/CodeGen/Mips/fastcc_byval.ll
+++ test/CodeGen/Mips/fastcc_byval.ll
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -O3 -relocation-model=pic -filetype=asm < %s | FileCheck %s
+
+%struct.str = type { i32, i32, [3 x i32*] }
+
+declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval nocapture readonly align 4 %s)
+
+define i32 @_Z1g3str(%struct.str* byval nocapture readonly align 4 %s) {
+; CHECK-LABEL: _Z1g3str:
+; CHECK:     sw  $7, [[OFFSET1:[0-9]+]]($sp)
+; CHECK:     sw  $6, [[OFFSET2:[0-9]+]]($sp)
+; CHECK:     sw  $5, [[OFFSET3:[0-9]+]]($sp)
+; CHECK:     sw  $4, [[OFFSET4:[0-9]+]]($sp)
+; CHECK-DAG: lw  ${{[0-9]+}}, [[OFFSET1]]($sp)
+; CHECK-DAG: lw  ${{[0-9]+}}, [[OFFSET2]]($sp)
+; CHECK-DAG: lw  ${{[0-9]+}}, [[OFFSET3]]($sp)
+; CHECK-DAG: lw  ${{[0-9]+}}, [[OFFSET4]]($sp)
+entry:
+  %ref.tmp = alloca %struct.str, align 4
+  %0 = bitcast %struct.str* %ref.tmp to i8*
+  call void @llvm.lifetime.start.p0i8(i64 20, i8* nonnull %0)
+  call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval nonnull align 4 %s)
+  %cl.sroa.3.0..sroa_idx2 = getelementptr inbounds %struct.str, %struct.str* %ref.tmp, i32 0, i32 1
+  %cl.sroa.3.0.copyload = load i32, i32* %cl.sroa.3.0..sroa_idx2, align 4
+  call void @llvm.lifetime.end.p0i8(i64 20, i8* nonnull %0)
+  ret i32 %cl.sroa.3.0.copyload
+}
+
+declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
+
+declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -4104,7 +4104,7 @@
 
   // Create frame object.
   EVT PtrTy = getPointerTy(DAG.getDataLayout());
-  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
+  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false);
   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
   InVals.push_back(FIN);
 
@@ -4122,7 +4122,7 @@
     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
                                    DAG.getConstant(Offset, DL, PtrTy));
     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
-                                 StorePtr, MachinePointerInfo(FuncArg, Offset));
+                                 StorePtr, MachinePointerInfo());
     OutChains.push_back(Store);
   }
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D37515.114004.patch
Type: text/x-patch
Size: 2550 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170906/8ce7458d/attachment.bin>