[PATCH] D36414: [X86][X87] Ensure x87 instructions are tagged as altering the FPSW reg

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL312629: [X86][X87] Ensure x87 instructions are tagged as altering the FPSW reg (authored by RKSimon).

Changed prior to commit:
  https://reviews.llvm.org/D36414?vs=110025&id=113980#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36414

Files:
  llvm/trunk/lib/Target/X86/X86InstrFPStack.td


Index: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td
@@ -615,36 +615,36 @@
 def FNSTSW16r : I<0xDF, MRM_E0,                  // AX = fp flags
                   (outs), (ins), "fnstsw\t{%ax|ax}",
                   [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>;
-
+let Defs = [FPSW] in
 def FNSTCW16m : I<0xD9, MRM7m,                   // [mem16] = X87 control world
                   (outs), (ins i16mem:$dst), "fnstcw\t$dst",
                   [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>;
 } // SchedRW
-let mayLoad = 1 in
+let Defs = [FPSW], mayLoad = 1 in
 def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
                   (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>,
                 Sched<[WriteLoad]>;
 
 // FPU control instructions
 let SchedRW = [WriteMicrocoded] in {
-let Defs = [FPSW] in
+let Defs = [FPSW] in {
 def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>;
 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
                 "ffree\t$reg", IIC_FFREE>;
 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg),
                 "ffreep\t$reg", IIC_FFREE>;
 
 // Clear exceptions
-
-let Defs = [FPSW] in
 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>;
+} // Defs = [FPSW]
 } // SchedRW
 
 // Operandless floating-point instructions for the disassembler.
 let SchedRW = [WriteMicrocoded] in {
-def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
-
 def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>;
+
+let Defs = [FPSW] in {
+def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
 def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>;
 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>;
 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>;
@@ -665,6 +665,7 @@
 def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>;
 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>;
 def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>;
+} // Defs = [FPSW]
 
 let Predicates = [HasFXSR] in {
   def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),


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