[PATCH] D37365: [x86] Enable f128 as a legal type in 64-bit mode if SSE is enabled rather than if MMX is enabled.

[Chih-Hung Hsieh via Phabricator via llvm-commits]

chh added a comment.

Okay, I see the change in extract_store.ll now.
The checks were not reduced.
The test mode +mmx was changed to +sse,
and expected output of +sse2, +sse4.1, +avx were changed.

With -mmmx -mno-sse, I can see a clang assertion fault following an error message:

    .... error: SSE register return with SSE disabled
  void foo(__float128 a, __float128 b, __float128 *c) {
       ^
  clang-5.0: .../llvm/lib/CodeGen/TargetRegisterInfo.cpp:173: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::MVT) const: Assertion `BestRC && "Couldn't find the register class"' failed.

Which target/plaftform needs "-mmmx -mno-sse"?
Which uses only mmx or sse?

I saw some other code that checked hasMMX() only,
so I added test cases with +sse2 and without +mmx.
I think they should not use the mmx registers.

How about making only the following change?

  if (Subtarget.is64Bit() && Subtarget.hasMMX())

to

  if (Subtarget.is64Bit() && Subtarget.hasMMX() && Subtarget.hasSSE1())

That will pass existing unit tests and your -mmx -mno-sse test case.


https://reviews.llvm.org/D37365