[PATCH] D19325: DAGCombine: (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Sorry for the late reply - this fell to the bottom of my todo pile for a while



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Comment at: test/CodeGen/AMDGPU/fneg-fabs.f16.ll:91-95
+; CI: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000
+; CI: v_lshlrev_b32_e32 [[SHL0:v[0-9]+]]
+; CI: v_or_b32_e32 v{{[0-9]+}}, [[SHL0]],
+; CI: v_lshlrev_b32_e32 [[SHL1:v[0-9]+]]
+; CI: v_or_b32_e32 v{{[0-9]+}}, [[SHL1]],
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tstellar wrote:
> Does this test generate extra shl instructions now, or did it generate those before the patch and there just weren't any check lines for it?
To confirm, the shifts were always there but the test didn't check for them


Repository:
  rL LLVM

https://reviews.llvm.org/D19325