[llvm] r312537 - [AMDGPU] Added extra test checks to make D19325 diff clearer

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Sep  5 07:32:06 2017
New Revision: 312537

URL: http://llvm.org/viewvc/llvm-project?rev=312537&view=rev
Log:
[AMDGPU] Added extra test checks to make D19325 diff clearer

Modified:
    llvm/trunk/test/CodeGen/AMDGPU/fneg-fabs.f16.ll

Modified: llvm/trunk/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fneg-fabs.f16.ll?rev=312537&r1=312536&r2=312537&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fneg-fabs.f16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fneg-fabs.f16.ll Tue Sep  5 07:32:06 2017
@@ -71,8 +71,10 @@ define amdgpu_kernel void @v_fneg_fabs_f
 ; FIXME: single bit op
 ; GCN-LABEL: {{^}}s_fneg_fabs_v2f16:
 ; CIVI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}}
+; CI: v_or_b32_e32 [[OR:v[0-9]+]], [[MASK]], v{{[0-9]+}}
+; CI: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[OR]]
+; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[SHL]]
 ; VI: v_mov_b32_e32 [[VMASK:v[0-9]+]], [[MASK]]
-; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
 ; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[VMASK]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
 ; CIVI: flat_store_dword
@@ -87,10 +89,14 @@ define amdgpu_kernel void @s_fneg_fabs_v
 
 ; GCN-LABEL: {{^}}fneg_fabs_v4f16:
 ; CIVI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}}
-; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
-; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
-; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
-; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
+; CI: v_or_b32_e32 [[OR00:v[0-9]+]], [[MASK]], v{{[0-9]+}}
+; CI: v_lshlrev_b32_e32 [[SHL0:v[0-9]+]], 16, [[OR00]]
+; CI: v_or_b32_e32 [[OR01:v[0-9]+]], v{{[0-9]+}}, [[SHL0]]
+; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], [[OR01]]
+; CI: v_or_b32_e32 [[OR10:v[0-9]+]], [[MASK]], v{{[0-9]+}}
+; CI: v_lshlrev_b32_e32 [[SHL1:v[0-9]+]], 16, [[OR10]]
+; CI: v_or_b32_e32 [[OR11:v[0-9]+]], v{{[0-9]+}}, [[SHL1]]
+; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], [[OR11]]
 ; VI: v_mov_b32_e32 [[VMASK:v[0-9]+]], [[MASK]]
 ; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[VMASK]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],