[PATCH] D37472: [ARM] Enable QADD and QSUB instruction selection

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

QADD/QSUB provide signed addition/subtraction that saturate the result between 2^31-1 and -2^31. These instructions are available on V5TE onwards cores in ARM mode, or Thumb cores that support the DSP extension.


https://reviews.llvm.org/D37472

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrInfo.td
  test/CodeGen/ARM/saturating-arith.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D37472.113845.patch
Type: text/x-patch
Size: 16007 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170905/49a4e5eb/attachment.bin>