[PATCH] D37328: [mips] Reordering callseq* nodes to be linear

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

+llvm-commits

That list should have been added when the patch was uploaded.

Can you re-upload the patch with full context: http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

Can you also add -verify-machineinstrs to test/CodeGen/Mips/largeimmprinting.ll ? This is the existing test case that breaks the machine verifier.



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Comment at: test/CodeGen/Mips/callseq_order.ll:18-52
+  call void @bar1(%struct.Str1* byval align 4 @s1)
+  ret void
+  ; CHECK-LABEL: Optimized legalized selection DAG: BB#0 'foo1:entry'
+  ; CHECK: t[[T0:[0-9]+]]: ch,glue = callseq_start
+  ; CHECK: t[[T1:[0-9]+]]: ch,glue = MipsISD::JmpLink t[[T0]]
+  ; CHECK: t[[T2:[0-9]+]]: ch,glue = callseq_end t[[T1]]
+  ; CHECK: t[[T3:[0-9]+]]: i{{(32|64)}},ch,glue = CopyFromReg t[[T2]]
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Rather than matching SelectionDAG's output, can you instead match the end output of -debug-only=isel and ensure that the output is a sequence of ADJCALLSTACKDOWN, ADJCALLSTACKUP which are not nested and match the memcpy calls where they occur.


Repository:
  rL LLVM

https://reviews.llvm.org/D37328