[llvm] r312321 - [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 1 03:47:25 PDT 2017
Author: olista01
Date: Fri Sep 1 03:47:25 2017
New Revision: 312321
URL: http://llvm.org/viewvc/llvm-project?rev=312321&view=rev
Log:
[ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB
This adds 2-operand assembly aliases for these instructions:
add r0, r1 => add r0, r0, r1
sub r0, r1 => sub r0, r0, r1
Previously this syntax was only accepted for Thumb2 targets, where the
wide versions of the instructions were used.
This patch allows the 2-operand syntax to be used for Thumb1 targets,
and selects the narrow encoding when it is used for Thumb2 targets.
Differential revision: https://reviews.llvm.org/D37377
Added:
llvm/trunk/test/MC/ARM/thumb-add-sub-width.s
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/test/MC/ARM/implicit-it-generation.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=312321&r1=312320&r2=312321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Sep 1 03:47:25 2017
@@ -997,6 +997,9 @@ let isAdd = 1 in {
}
}
+def : tInstAlias <"add${s}${p} $Rdn, $Rm",
+ (tADDrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
+
def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",
(tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;
def : tInstSubst<"sub${s}${p} $rdn, $imm",
@@ -1286,6 +1289,9 @@ def tSUBrr : // A8.6.
[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
Sched<[WriteALU]>;
+def : tInstAlias <"sub${s}${p} $Rdn, $Rm",
+ (tSUBrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
+
/// Similar to the above except these set the 's' bit so the
/// instruction modifies the CPSR register.
///
Modified: llvm/trunk/test/MC/ARM/implicit-it-generation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/implicit-it-generation.s?rev=312321&r1=312320&r2=312321&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/implicit-it-generation.s (original)
+++ llvm/trunk/test/MC/ARM/implicit-it-generation.s Fri Sep 1 03:47:25 2017
@@ -394,12 +394,12 @@ label:
.endr
@ CHECK: itete eq
@ CHECK: addeq r0, r1
-@ CHECK: subne.w r0, r0, r1
+@ CHECK: subne r0, r0, r1
@ CHECK: addeq r0, r1
-@ CHECK: subne.w r0, r0, r1
+@ CHECK: subne r0, r0, r1
@ CHECK: ite eq
@ CHECK: addeq r0, r1
-@ CHECK: subne.w r0, r0, r1
+@ CHECK: subne r0, r0, r1
@ Flush at end of file
.section test99
Added: llvm/trunk/test/MC/ARM/thumb-add-sub-width.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-add-sub-width.s?rev=312321&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-add-sub-width.s (added)
+++ llvm/trunk/test/MC/ARM/thumb-add-sub-width.s Fri Sep 1 03:47:25 2017
@@ -0,0 +1,70 @@
+// RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
+
+ .text
+ .thumb
+
+ // Check that the correct encoding of the add and sub instructions is
+ // selected, for all combinations of flag-setting, condition and 2- or
+ // 3-operand syntax.
+
+ .arch armv6-m
+ add r0, r0, r1 // T2
+ add r0, r1 // T2
+ adds r0, r0, r1 // T1
+ adds r0, r1 // T1
+// CHECK: add r0, r1 @ encoding: [0x08,0x44]
+// CHECK: add r0, r1 @ encoding: [0x08,0x44]
+// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
+// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
+
+ .arch armv7-m
+ add r0, r0, r1 // T2, T3
+ add r0, r1 // T2, T3
+ adds r0, r0, r1 // T1, T3
+ adds r0, r1 // T1, T3
+// CHECK: add r0, r1 @ encoding: [0x08,0x44]
+// CHECK: add r0, r1 @ encoding: [0x08,0x44]
+// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
+// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
+
+ itttt eq
+// CHECK: itttt eq @ encoding: [0x01,0xbf]
+ addeq r0, r0, r1 // T1, T2, T3
+ addeq r0, r1 // T2, T1, T3
+ addseq r0, r0, r1 // T3
+ addseq r0, r1 // T3
+ // NOTE: Both T1 and T2 are valid for these two instructions, which one is
+ // the preferred varies depending on whether the 2- or 3-operand syntax was
+ // used.
+// CHECK: addeq r0, r0, r1 @ encoding: [0x40,0x18]
+// CHECK: addeq r0, r1 @ encoding: [0x08,0x44]
+// CHECK: addseq.w r0, r0, r1 @ encoding: [0x10,0xeb,0x01,0x00]
+// CHECK: addseq.w r0, r0, r1 @ encoding: [0x10,0xeb,0x01,0x00]
+
+ .arch armv6-m
+ // NOTE: There is no non-flag-setting sub instruction for v6-M
+ subs r0, r0, r1 // T1, T2
+ subs r0, r1 // T1, T2
+// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
+// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
+
+ .arch armv7-m
+ sub r0, r0, r1 // T2
+ sub r0, r1 // T2
+ subs r0, r0, r1 // T1, T2
+ subs r0, r1 // T1, T2
+// CHECK: sub.w r0, r0, r1 @ encoding: [0xa0,0xeb,0x01,0x00]
+// CHECK: sub.w r0, r0, r1 @ encoding: [0xa0,0xeb,0x01,0x00]
+// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
+// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
+
+ itttt eq
+// CHECK: itttt eq @ encoding: [0x01,0xbf]
+ subeq r0, r0, r1 // T1, T2
+ subeq r0, r1 // T1, T2
+ subseq r0, r0, r1 // T2
+ subseq r0, r1 // T2
+// CHECK: subeq r0, r0, r1 @ encoding: [0x40,0x1a]
+// CHECK: subeq r0, r0, r1 @ encoding: [0x40,0x1a]
+// CHECK: subseq.w r0, r0, r1 @ encoding: [0xb0,0xeb,0x01,0x00]
+// CHECK: subseq.w r0, r0, r1 @ encoding: [0xb0,0xeb,0x01,0x00]
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