[llvm] r312279 - [x86] add more tests for horizontal ops; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 31 13:59:25 PDT 2017
Author: spatel
Date: Thu Aug 31 13:59:25 2017
New Revision: 312279
URL: http://llvm.org/viewvc/llvm-project?rev=312279&view=rev
Log:
[x86] add more tests for horizontal ops; NFC
Added:
llvm/trunk/test/CodeGen/X86/haddsub-shuf.ll
Modified:
llvm/trunk/test/CodeGen/X86/haddsub.ll
Added: llvm/trunk/test/CodeGen/X86/haddsub-shuf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-shuf.ll?rev=312279&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/haddsub-shuf.ll (added)
+++ llvm/trunk/test/CodeGen/X86/haddsub-shuf.ll Thu Aug 31 13:59:25 2017
@@ -0,0 +1,159 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
+
+; The next 8 tests check for matching the horizontal op and eliminating the shuffle.
+; PR34111 - https://bugs.llvm.org/show_bug.cgi?id=34111
+
+define <4 x float> @hadd_v4f32(<4 x float> %a) {
+; SSSE3-LABEL: hadd_v4f32:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: haddps %xmm0, %xmm0
+; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hadd_v4f32:
+; AVX: # BB#0:
+; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT: retq
+ %a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>
+ %a13 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 1, i32 3>
+ %hop = fadd <2 x float> %a02, %a13
+ %shuf = shufflevector <2 x float> %hop, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
+ ret <4 x float> %shuf
+}
+
+define <4 x float> @hsub_v4f32(<4 x float> %a) {
+; SSSE3-LABEL: hsub_v4f32:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: hsubps %xmm0, %xmm0
+; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hsub_v4f32:
+; AVX: # BB#0:
+; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT: retq
+ %a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>
+ %a13 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 1, i32 3>
+ %hop = fsub <2 x float> %a02, %a13
+ %shuf = shufflevector <2 x float> %hop, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+ ret <4 x float> %shuf
+}
+
+define <2 x double> @hadd_v2f64(<2 x double> %a) {
+; SSSE3-LABEL: hadd_v2f64:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: haddpd %xmm0, %xmm0
+; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hadd_v2f64:
+; AVX: # BB#0:
+; AVX-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT: retq
+ %a0 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
+ %a1 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
+ %hop = fadd <2 x double> %a0, %a1
+ %shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x double> %shuf
+}
+
+define <2 x double> @hsub_v2f64(<2 x double> %a) {
+; SSSE3-LABEL: hsub_v2f64:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: hsubpd %xmm0, %xmm0
+; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hsub_v2f64:
+; AVX: # BB#0:
+; AVX-NEXT: vhsubpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT: retq
+ %a0 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
+ %a1 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
+ %hop = fsub <2 x double> %a0, %a1
+ %shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 undef, i32 0>
+ ret <2 x double> %shuf
+}
+
+define <4 x i32> @hadd_v4i32(<4 x i32> %a) {
+; SSSE3-LABEL: hadd_v4i32:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: phaddd %xmm0, %xmm0
+; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hadd_v4i32:
+; AVX: # BB#0:
+; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX-NEXT: retq
+ %a02 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
+ %a13 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
+ %hop = add <4 x i32> %a02, %a13
+ %shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 1>
+ ret <4 x i32> %shuf
+}
+
+define <4 x i32> @hsub_v4i32(<4 x i32> %a) {
+; SSSE3-LABEL: hsub_v4i32:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: phsubd %xmm0, %xmm0
+; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hsub_v4i32:
+; AVX: # BB#0:
+; AVX-NEXT: vphsubd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX-NEXT: retq
+ %a02 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
+ %a13 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
+ %hop = sub <4 x i32> %a02, %a13
+ %shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <4 x i32> <i32 undef, i32 1, i32 0, i32 undef>
+ ret <4 x i32> %shuf
+}
+
+define <8 x i16> @hadd_v8i16(<8 x i16> %a) {
+; SSSE3-LABEL: hadd_v8i16:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: phaddw %xmm0, %xmm0
+; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hadd_v8i16:
+; AVX: # BB#0:
+; AVX-NEXT: vphaddw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX-NEXT: retq
+ %a0246 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
+ %a1357 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
+ %hop = add <8 x i16> %a0246, %a1357
+ %shuf = shufflevector <8 x i16> %hop, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
+ ret <8 x i16> %shuf
+}
+
+define <8 x i16> @hsub_v8i16(<8 x i16> %a) {
+; SSSE3-LABEL: hsub_v8i16:
+; SSSE3: # BB#0:
+; SSSE3-NEXT: phsubw %xmm0, %xmm0
+; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; SSSE3-NEXT: retq
+;
+; AVX-LABEL: hsub_v8i16:
+; AVX: # BB#0:
+; AVX-NEXT: vphsubw %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; AVX-NEXT: retq
+ %a0246 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
+ %a1357 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
+ %hop = sub <8 x i16> %a0246, %a1357
+ %shuf = shufflevector <8 x i16> %hop, <8 x i16> undef, <8 x i32> <i32 0, i32 undef, i32 2, i32 undef, i32 undef, i32 1, i32 undef, i32 3>
+ ret <8 x i16> %shuf
+}
+
Modified: llvm/trunk/test/CodeGen/X86/haddsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub.ll?rev=312279&r1=312278&r2=312279&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/haddsub.ll (original)
+++ llvm/trunk/test/CodeGen/X86/haddsub.ll Thu Aug 31 13:59:25 2017
@@ -398,22 +398,3 @@ define <2 x float> @haddps_v2f32(<4 x fl
ret <2 x float> %res1
}
-define <4 x float> @PR34111(<4 x float> %a) {
-; SSE3-LABEL: PR34111:
-; SSE3: # BB#0:
-; SSE3-NEXT: haddps %xmm0, %xmm0
-; SSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
-; SSE3-NEXT: retq
-;
-; AVX-LABEL: PR34111:
-; AVX: # BB#0:
-; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
-; AVX-NEXT: retq
- %a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>
- %a13 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 1, i32 3>
- %add = fadd <2 x float> %a02, %a13
- %hadd = shufflevector <2 x float> %add, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
- ret <4 x float> %hadd
-}
-
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