[PATCH] D37068: [AArch64] IDSAR6 register assembler support

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL312225: [AArch64] IDSAR6 register assembler support (authored by sam_parker).

Changed prior to commit:
  https://reviews.llvm.org/D37068?vs=113210&id=113369#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D37068

Files:
  llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
  llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt


Index: llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: mrs x0, ID_ISAR6_EL1
+0xe0,0x02,0x38,0xd5
Index: llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
+++ llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+  mrs x0, ID_ISAR6_EL1
+// CHECK: mrs x0, ID_ISAR6_EL1        // encoding: [0xe0,0x02,0x38,0xd5]
+// CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, ID_ISAR6_EL1
+// CHECK-REQ-NEXT:         ^
Index: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
@@ -342,6 +342,9 @@
 def : ROSysReg<"ID_ISAR3_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b011>;
 def : ROSysReg<"ID_ISAR4_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b100>;
 def : ROSysReg<"ID_ISAR5_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b101>;
+def : ROSysReg<"ID_ISAR6_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b111> {
+  let Requires = [{ {AArch64::HasV8_2aOps} }];
+}
 def : ROSysReg<"ID_AA64PFR0_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b000>;
 def : ROSysReg<"ID_AA64PFR1_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b001>;
 def : ROSysReg<"ID_AA64DFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b000>;


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