[llvm] r312225 - [AArch64] IDSAR6 register assembler support

[Sam Parker via llvm-commits]

Author: sam_parker
Date: Thu Aug 31 01:36:45 2017
New Revision: 312225

URL: http://llvm.org/viewvc/llvm-project?rev=312225&view=rev
Log:
[AArch64] IDSAR6 register assembler support

The IDSAR6 system register has been introduced to identify the
v8.3-a Javascript data type conversion and v8.2-a dot product
support.

Differential Revision: https://reviews.llvm.org/D37068

Added:
    llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
    llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=312225&r1=312224&r2=312225&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Thu Aug 31 01:36:45 2017
@@ -342,6 +342,9 @@ def : ROSysReg<"ID_ISAR2_EL1",       0b1
 def : ROSysReg<"ID_ISAR3_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b011>;
 def : ROSysReg<"ID_ISAR4_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b100>;
 def : ROSysReg<"ID_ISAR5_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b101>;
+def : ROSysReg<"ID_ISAR6_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b111> {
+  let Requires = [{ {AArch64::HasV8_2aOps} }];
+}
 def : ROSysReg<"ID_AA64PFR0_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b000>;
 def : ROSysReg<"ID_AA64PFR1_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b001>;
 def : ROSysReg<"ID_AA64DFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b000>;

Added: llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s?rev=312225&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s Thu Aug 31 01:36:45 2017
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+  mrs x0, ID_ISAR6_EL1
+// CHECK: mrs x0, ID_ISAR6_EL1        // encoding: [0xe0,0x02,0x38,0xd5]
+// CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, ID_ISAR6_EL1
+// CHECK-REQ-NEXT:         ^

Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt?rev=312225&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt Thu Aug 31 01:36:45 2017
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: mrs x0, ID_ISAR6_EL1
+0xe0,0x02,0x38,0xd5